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11 - /14 - bit, 5.6 gsps, rf digital - to - analog converter data sheet ad9119 / ad9129 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features dac update rate: up to 5.6 gsps direct rf synthesis at 2.8 gsps data rate dc to 1.4 ghz in baseband mode dc to 1.0 ghz in 2 interpolation mode 1.4 ghz to 4.2 ghz in mix - mode bypassable 2 interpolation excellent dynamic performance supports docs is 3.0 wideband aclr/harmonic performance 8 qam carriers: aclr > 6 5 dbc industry - leading single/multicarrier if or rf synthesis 4- carrier w - cdma aclr at 2457.6 msps f out = 900 mhz, aclr = 71 dbc (b aseband mode) f out = 2100 mhz, aclr = 68 dbc (mix - mode) f out = 2700 mhz, aclr = 67 dbc (mix - mode) dual - port lvds and dhstl data interface up to 1.4 gsps operation source synchronous ddr clocking with parity bit low power: 1. 0 w at 2.8 gsps (1.3 w at 5.6 gsps) applications broadband communications systems cmts/v od wireless infrastructure: w- cdma , lte, point - to - point instrumentation, automatic test equipment (ate) radar s , jammers functional block dia gram sdo sdio sclk cs dci_x data assembler spi reset tx dac core data latch ioutp ioutn irq 4 fifo 2 baseband mode mix- mode frm_x (frame/ parity) ad9129 clock distribution vref i250u lvds ddr receiver lvds ddr receiver p1_d[13:0]p, p1_d[13:0]n p0_d[13:0]p, p0_d[13:0]n dl l 1.2v pll dco_x normal 11 149-001 dacclk_x dcr figure 1. general description the ad9 119 / ad9129 are high performance, 11 -/ 14 - bit rf digital - to - analog converters ( dacs ) support ing data rates up to 2.8 gsps. the dac core is based on a quad - switch architecture that enables dual - edge clocking operation, effectively increasing the dac update rate t o 5.6 gsps when configured for mix -m ode ? or 2 interpolation. the high dynamic range and bandwidth enable multicarrier generation up to 4.2 ghz. in baseband mode, wide bandwidth capability combines with hi gh dynamic range to support from 1 to 158 contiguous carriers for catv infrastructure applications. a choice of two optional 2 interpolation filters is available to simplify the postreconstruction filter by effectively increasing the dac update rate by a factor of 2. in mix - mode operation, the ad9119 / ad9129 can reconstruct rf carriers in th e second and third nyquist zone while still maintaining exceptional dynamic r ange up to 4.2 ghz. the high performance nmos dac core features a quad - switch architecture that enables industry - leading direct rf synthesis performance with minimal loss in output power. the output current can be programmed over a range of 9.5 ma to 34.4 ma. the ad9119 / ad9129 include several features that may further simplify system integration. a dual - port, source synchronous lvds interface simplifies the data inte rface to a host fpga/asic. a differential frame/parity bit is also included to monitor the integrity of the interface. on - chip delay locked loops (dlls) are used to optimize timing between different clock domains. a serial peripheral interface (spi) is use d to configure the ad9119 / ad9129 and monitor the status of readback registers. the ad9119 / ad9129 is manufactured on a 0.18 m cmos process and operates from +1.8 v and ?1.5 v supplies. it is supplied in a 160 - ball chip scale package ball grid array. product highlights 1. high dynamic range and signal r econstruction bandwidth sup port rf signal synthesis of up to 4.2 ghz. 2. dual - port interface with double data rate (ddr) lvds data receivers supports 2800 msps maximum conversion rate. 3. manufactured on a cmos process; a p roprietary switching technique enhances dynamic performance.
ad9119/ad9129 data sheet rev. 0 | page 2 of 68 tab le of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 dc specifications ......................................................................... 3 lvds digital specifications ........................................................ 4 hstl digital specifications ........................................................ 4 serial port and cmos pin specifications ................................. 5 ac specifications .......................................................................... 6 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 typical performance characteristics ........................................... 12 ad9119 ........................................................................................ 12 ad9129 ........................................................................................ 22 terminology .................................................................................... 35 serial communications port overview ....................................... 36 serial peripheral interface (spi) ............................................... 36 general operation of the spi .................................................... 36 instruction mode (8 - bit instruction) ...................................... 36 serial peripheral interface pin descriptions .......................... 36 msb/lsb transfers .................................................................... 37 serial port configuration .......................................................... 37 theory of operation ...................................................................... 38 lvds data port interface .......................................................... 39 digital datapath description ................................................... 42 interrupt requests ...................................................................... 46 interface timing validation .......................................................... 48 sample error detection (sed) operation .............................. 48 sed e xample ............................................................................... 48 analog interface considerations .................................................. 49 analog modes of operation ..................................................... 49 clock input .................................................................................. 50 pll ............................................................................................... 50 voltage reference ....................................................................... 51 analog outp uts .......................................................................... 51 start - up sequence ...................................................................... 54 device configuration registers .................................................... 55 de vice configuration register map ........................................ 55 device configuration register descriptions .......................... 56 outline dimensions ....................................................................... 66 ordering guide .......................................................................... 66 revision history 1/13 revision 0: initial version
data sheet ad9119/ad9129 rev. 0 | page 3 of 68 specifications dc specifications vdda = vdd = 1.8 v, vssa = ?1.5 v, i outf s = 33 ma , t a = ? 40 c to + 85 c. table 1. ad9119 ad9129 parameter min typ max min typ max unit resolution 11 14 bits accuracy integral nonlinearity (inl) 0.2 1.4 lsb d ifferential nonlinearity (dnl) 0.15 1.1 lsb analog outputs gain error (with internal reference) +2.5 +2.5 % full - scale output current maximum 33.4 34.2 34.9 33.4 34.2 34.9 ma full - scale output current minimum 9.1 9.4 9.6 9.1 9.4 9.6 ma output compliance range 1.5 2.5 1.5 2.5 v output impedance 1 dac clock input (dacclk_p, dacclk_n) differential peak -to - peak voltage 0.4 1 2 0.4 1 2 v common - mode voltage 1.2 1.2 v temperature drift gain 60 60 p pm/c reference voltage 20 20 ppm/c reference internal reference voltage 1.0 1.0 v output resistance 5 5 k? analog supply voltages vdda 1.70 1.80 1.90 1.70 1.80 1.90 v vssa ?1.4 ?1.5 ?1.6 ?1.4 ?1.5 ?1.6 v digital su pply voltages vdd 1.70 1.8 1.90 1.70 1.8 1.90 v fir40 enabled, dacclk > 2600 msps 1.8 1.9 2.0 1.8 1.9 2.0 v supply currents and power dissipation, 2.3 gsps (normal mode) i vdda 202 209 202 209 ma i vssa 53 54 53 54 ma i dvdd 30 7 327 307 327 ma power dissipation normal mode 1.0 1.05 1.0 1.05 w fir25 enabled 1.1 7 1.2 4 1.1 7 1.2 4 w fir40 enabled 1. 3 1. 4 1. 3 1. 4 w reduced power mode, power - down enabled ( register 0x01 = 0xef) i vdda 7.6 7.6 ma i vssa 6 6 a i vdd 0.4 0.4 ma supply currents and power dissipation, 2.8 gsps (normal mode) i vdda 230 230 ma i vssa 53 53 ma i dvdd 336 336 ma power dissipatio n ( normal mode ) 1.1 1.1 w 1 for more information about output impedance, see the output stage configuration section.
ad9119/ad9129 data sheet rev. 0 | page 4 of 68 lvd s digital specificat ions vdda = vdd = 1.8 v, vssa = ?1.5 v, i outf s = 33 ma , t a = ? 40 c to + 85 c . lvds drivers and receivers are compatible with the ieee standard 1596.3 - 1996, unless otherwise noted. table 2. parameter symbol test conditions/comments min typ max unit lvds data inpu ts (p1_d[13:0]p, p1_d[13:0]n, p0_d[13:0]p, p0_d[13:0]n) px_dxp = v ia , px_dxn = v ib input voltage range v ia , v ib 825 1575 mv input differential threshold v idth ?100 +100 mv input differential hysteresis v idthh ? v idthl 20 mv receiv er differential input impedance r in 80 120 ? lvds input rate 1400 msps input capacitance 1.2 pf lvds clock inputs (dci_p, dci_n) dci_p = v ia , dci_n = v ib input voltage range v ia , v ib 825 1575 mv input differential threshold v i dth ?225 +225 mv input differential hysteresis v idthh ? v idthl 20 mv receiver differential input impedance r in 80 120 ? maximum clock rate 700 mhz lvds clock outputs (dco_p, dco_n) dco_p = v oa , dco_n = v ob , 100 ? termination ou tput voltage high v oa , v ob 1375 mv output voltage low v oa , v ob 1025 mv output differential voltage |v oa |, |v ob | register 0x7c [7:6] = 01b (default) 200 225 250 mv output offset voltage v os 1150 1250 mv output impedance, single - ended r o 80 1 00 120 ? r o mismatch between a and b ?r o 10 % change in |v od | between setting 0 and setting 1 |?v od | 25 mv change in v os between setting 0 and setting 1 ?v os 25 mv output current driver shorted to ground i sa , i sb 20 ma drivers shorted together i sab 4 ma power - off output leakage |i xa |, |i xb | 10 a maximum clock rate 700 mhz hstl digital specifi cations vdda = vdd = 1.8 v, vssa = ?1.5 v, i outf s = 33 ma , t a = ? 40 c to + 85 c. hstl receiver levels are compatible with the eia/ jedec jesd8 - 6 standard, unless otherwise noted. table 3. parameter symbol test comments/conditions min typ max unit hstl data inputs (p1_d[13:0]p, p1_d[13:0]n, p0_d[13:0]p, p0_d[13:0]n) px_dxp = v ia , px_dxn = v ib common -mo de input voltage range v ia , v ib 0.68 0.9 v differential input voltage 200 mv receiver differential input impedance r in 80 120 ? hstl input rate 1400 msps input capacitance 1.2 pf hstl clock input (dci_p, dci_n) dci_p = v ia , dci_n = v ib common - mode input voltage range v ia , v ib 0.68 0.9 mv differential input voltage 450 mv receiver differential input impedance r in 80 120 ? maximum clock rate 700 mhz
data sheet ad9119/ad9129 rev. 0 | page 5 of 68 serial port and cmos pin specifications vdda = vdd = 1.8 v, vssa = ?1.5 v, i outf s = 33 ma , t a = ? 40 c to + 85 c. table 4 . parameter symbol test comments/conditions min typ max unit write operation see figure 126 sclk clock rate f sclk , 1/t sclk 20 mhz sclk clock high t high 20 ns sclk clock low t low 20 ns sdio to sclk setup time t ds 10 ns sclk to sdio hold time t dh 5 ns cs to sclk setup time t s 10 ns sclk to cs hold time t h 5 ns read operation see figure 127 sclk clock rate f sclk , 1/t sclk 20 mhz sclk clock high t high 20 ns sclk clock low t low 20 ns sdio to sclk setup time t ds 10 ns sclk to sdio hold time t dh 5 ns cs to sclk setup time t s 10 ns sclk to sdio (or sdo) data valid time t dv 10 ns cs to sdio (or sdo) output val id to high -z t ez 2 inputs (sdi, sdio, sclk, cs ) voltage in high v ih 1.2 1.8 v voltage in low v il 0 0.4 v current in high i ih +75 a current in low i il ?150 a outputs (sdio, sync) voltage out high v oh 1.3 2.0 v voltage out low v ol 0 0.3 v current out high i oh 4 ma current out low i ol 4 ma
ad9119/ad9129 data sheet rev. 0 | page 6 of 68 ac specifications vdda = vdd = 1.8 v, vssa = ?1.5 v, i outf s = 33 ma , t a = ? 40 c to + 85 c, un less otherwise noted. table 5. ad9119 ad9129 parameter min typ max min typ max unit dynamic performance dac update rate (dacclk _x inputs) normal mode, fir25 enabled, or fir40 enabled with vdd = 1.9 v 1400 280 0 1400 2800 msps fir40 filter enabled, vdd = 1.8 v 1400 2600 1400 2600 msps adjusted dac update rate 1 1400 2800 1400 2800 msps output settling time to 0.1% 13 13 ns spurious - free dynamic range (sfdr) f dac = 2600 msps f out = 1 00 mhz ? 76 ?76 dbc f out = 350 mhz ? 65 ?65 dbc f out = 550 mhz ? 63 ?64 dbc f out = 950 mhz ? 55 ?55 dbc two - tone intermodulation distortion (imd) f dac = 2600 msps, f out2 = f out1 + 1.4 mhz f out = 100 mhz ? 82 ?86 db c f out = 350 mhz ? 78 ?85 dbc f out = 550 mhz ? 73 ?83 dbc f out = 950 mhz ? 67 ?76 dbc noise spectral density (nsd) single tone, f dac = 2800 msps f out = 100 mhz ? 157 ?166 dbm/hz f out = 350mhz ? 157 ?162 dbm/hz f out = 550 mhz ? 155 ?158 dbm/hz f out = 850 mhz ? 154 ?157 dbm/hz docsis aclr perfor mance (50 mhz to 1000 mhz) at 6 mhz offset f dac = 2782 msps 8 contiguous carriers 64 64 dbc 16 contiguous carriers 62 63 dbc 32 contigu ous carriers 60 61 dbc w- cdma aclr (single carrier) adjacent channel f dac = 2605.056 msps , f out = 750 mhz 75 75 dbc f dac = 2605.056 msps, f out = 950 mhz 74 74 dbc f dac = 2605.056 msps, f out = 1700 mhz (mix - mode) 73.5 73.5 dbc f dac = 2605.056 msps, f out = 2100 mhz (mix - mode) 69 69 dbc alternate adjacent channel f dac = 2605.056 msps, f out = 750 mhz 80 80 dbc f dac = 2605.056 msps, f out = 950 mhz 78 78 dbc f dac = 2605.056 msps, f out = 1700 mhz (mix - mode) 74 74 dbc f dac = 2605.056 msps, f out = 2100 mhz (mix - mode) 72 72 dbc 1 adjusted dac updat e rate is calculated as f dac divided by the minimum required interpolation factor. for the ad9119 / ad9129 , the minimum interpolation factor is 1. thus, with f dac = 280 0 msps, f dac adjusted = 2800 msps.
data sheet ad9119/ad9129 rev. 0 | page 7 of 68 absolute maximum rat ings table 6. parameter rating dci, dco to vss ?0.3 v to vdd + 0.3 v lvds data inputs to vss ?0.3 v to vdd + 0.3 v ioutp, i outn to vssa vssa ? 0.3v to +2.5v i250u, vref to vssa vssa ? 0.3 v to vdda + 0.3 v irq, cs , sclk, sdo, sdio, reset, sync to vss ?0.3 v to vdd + 0.3 v junction temperature 150c operating temperature range ?40c to +85c storage temp erature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in t he operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered i n a circuit board for surface - mount packages. table 7 . thermal resistance package type ja jc unit 160- ball csp_bga 31.2 7.0 c/w 1 1 with no airflow movement. esd caution
ad9119/ad9129 data sheet rev. 0 | page 8 of 68 pin configurations and function descript ions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a b c d e f g h j k l m n p vref vssa vdda sh ioutp ioutn vdda sh vdda vdda vdda vssc vssc vssc vdda i250u vssa vssa vssa vdda sh vdda dacclk_n vss vss vss vss vss vss vss vss cs sclk dci_p dci_n frm_p frm_n p1_d0p p1_d1p p1_d2p p1_d3p p1_d4p p1_d5p p1_d6p p1_d7p p1_d8p p1_d9p p1_d10p vssa vssa vssc vdda vdda vssc vdda vdda vdda vssa vdda sh vss vssc vdda vdda vssc vss vss vss vss vssc vdda vdda vssc vssc vssc vssc vssc vssc vssc dacclk_p vdda vdda vssc vss vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vssc vss vss vss irq reset vss vss vdd vdd sdo sdio p1_d0n p1_d1n p1_d2n p1_d3n p1_d4n p1_d5n p1_d6n p1_d7n p1_d8n p1_d9n p1_d10n p0_d0p p0_d1p p0_d2p p0_d3p p0_d4p p0_d5p p0_d6p p0_d7p p0_d8p p0_d9p p0_d10p p0_d0n p0_d1n p0_d2n p0_d3n p0_d4n p0_d5n p0_d6n p0_d7n p0_d8n p0_d9n p0_d10n vdda vdda vssa vdda vdda vdda vssc vssc vssc dco_p dco_n ad9119 notes 1. nc = no connect. do not connect to this pin. sync nc nc nc nc nc nc nc nc nc nc nc nc 11 149-002 f igure 2. ad9119 pin configuration table 8 . ad9119 pin function descriptions pin no. mnemonic description a1 i250u nominal 1.0 v reference. tie this pin to vssa via a 4.0 k? resistor to generate a 250 a reference current. a2 vref voltage reference input/output. decouple to vssa with a 1 nf capacitor. a3, a4, b3, b4, b5, c4, c5, c6 vssa ?1.5 v analog supply voltage input. a5, a8, b6, b7 vdda sh +1.8 v analog supply sh ield. tie these pins to vdda at the dac. a9, a10, a11, b1, b2, b8, b9, b10, b11, c2, c3, c7, c8, c9, c10, d2, d3, d4, d7, e1, e2 vdda +1.8 v analog supply voltage input.
data sheet ad9119/ad9129 rev. 0 | page 9 of 68 pin no. mnemonic description g12, g13, g14, h11, h12, h13, h14, j3, j4, j11, j12, j13, j14 vdd +1.8 v digital supply voltage input. c13, c14, d12, d13, d14, e11, e12, e13, e14, f11, f12, f13, f14, g1, g2, g3, g11, h3, h4 vss +1.8 v digital supply return. a12, a13, a14, b12, b13, c11, c12, d5, d6, d8, d9, d10, d11, e3, e4, f1, f2, f3, f4, g4 vssc analog supply return. a6 ioutp dac positive current output source. a7 ioutn dac negative current output source. b14 sync synchronization signal output. c1, d1 dacclk_n, dacclk_p negative/positive dac clock input. h1 reset reset input. active high. if unused, tie this pin to vss. h2 irq interrupt request open drain output. active high. pull up this pin to vdd with a 1 k? resistor. j1 sdio serial port data input/output. j2 sdo serial port data output. k1 sclk serial port clock input. k2 cs serial port enable input. k3, k4 dci_p, dci_n positive, negative data clock input (dci). k11, k12 d c o _ p, dc o_n positive, negative data clock output (dco). k13, k14 frm_p, frm_n positive, negative data frame/parity signal (frame/parity). l1, m1 nc, nc no connect. do not connect to this pin. l2, m2 nc, nc no connect. do not connect to this pin. l3, m3 nc, nc no connect. do not connect to this pin. l4, m4 p1_d0p, p1_d0n data port 1 positive/negative data input bit 0. l5, m5 p1_d1p, p1_d1n data port 1 positive/negative data input bit 1. l6, m6 p1_d2p, p1_d2n data port 1 positive/negative data input bit 2. l7, m7 p1_d3p, p1_d3n data port 1 positive/negative data input bit 3. l8, m8 p1_d4p, p1_d4n data port 1 positive/negative data input bit 4. l9, m9 p1_d5p, p1_d5n data port 1 positive/negative data input bit 5. l10, m10 p1_d6p, p1_d6n data port 1 po sitive/negative data input bit 6. l11, m11 p1_d7p, p1_d7n data port 1 positive/negative data input bit 7. l12,m12 p1_d8p, p1_d8n data port 1 positive/negative data input bit 8. l13, m13 p1_d9p, p1_d9n data port 1 positive/negative data input bit 9. l14, m14 p1_d10p, p1_d10n data port 1 positive/negative data input bit 10. n1, p1 nc, nc no connect. do not connect to this pin. n2, p2 nc, nc no connect. do not connect to this pin. n3, p3 nc, nc no connect. do not connect to this pin. n4, p4 p0_d0p, p0_d0n data port 0 positive/negative data input bit 0. n5, p5 p0_d1p, p0_d1n data port 0 positive/negative data input bit 1. n6, p6 p0_d2p, p0_d2n data port 0 positive/negative data input bit 2. n7, p7 p0_d3p, p0_d3n data port 0 positive/negative da ta input bit 3. n8, p8 p0_d4p, p0_d4n data port 0 positive/negative data input bit 4. n9, p9 p0_d5p, p0_d5n data port 0 positive/negative data input bit 5. n10, p10 p0_d6p, p0_d6n data port 0 positive/negative data input bit 6. n11, p11 p0_d7p, p0_ d7n data port 0 positive/negative data input bit 7. n12, p12 p0_d8p, p0_d8n data port 0 positive/negative data input bit 8. n13, p13 p0_d9p, p0_d9n data port 0 positive/negative data input bit 9. n14, p14 p0_d10p, p0_d10n data port 0 positive/negativ e data input bit 10.
ad9119/ad9129 data sheet rev. 0 | page 10 of 68 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a b c d e f g h j k l m n p vref vssa vdda sh ioutp ioutn vdda sh vdda vdda vdda vssc vssc vssc vdda i250u vssa vssa vssa vdda sh vdda dacclk_n vss vss vss vss vss vss vss vss sclk dci_p dci_n frm_p frm_n p1_d3p p1_d4p p1_d5p p1_d6p p1_d7p p1_d8p p1_d9p p1_d10p p1_d11p p1_d12p p1_d13p vssa vssa vssc vdda vdda vssc vdda vdda vdda vssa vdda sh vss vssc vdda vdda vssc vss vss vss vss vssc vdda vdda vssc vssc vssc vssc vssc vssc vssc dacclk_p vdda vdda vssc vss vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vssc vss vss vss irq reset vss vss vdd vdd sdo sdio p1_d3n p1_d4n p1_d5n p1_d6n p1_d7n p1_d8n p1_d9n p1_d10n p1_d11n p1_d12n p1_d13n p0_d3p p0_d4p p0_d5p p0_d6p p0_d7p p0_d8p p0_d9p p0_d10p p0_d11p p0_d12p p0_d13p p0_d3n p0_d4n p0_d5n p0_d6n p0_d7n p0_d8n p0_d9n p0_d10n p0_d11n p0_d12n p0_d13n vdda vdda vssa vdda vdda vdda vssc vssc vssc dco_p dco_n ad9129 sync p1_d0p p1_d1p p1_d2p p1_d0n p1_d1n p1_d2n p0_d0p p0_d1p p0_d2p p0_d0n p0_d1n p0_d2n 11 149-003 cs figure 3. ad9129 pin configuration table 9 . ad9129 pin function descriptions pin no. mn emonic description a1 i250u nominal 1.0 v reference. tie this pin to vssa via a 4.0 k? resistor to generate a 250 a reference current. a2 vref voltage reference input/output. decouple to vssa with a 1 nf capacitor. a3, a4, b3, b4, b5, c4, c5, c6 vssa ?1.5 v analog supply voltage input. a5, a8, b6, b7 vdda sh +1.8 v analog supply sh ield. tie these pins to vdda at the dac. a9, a10, a11, b1, b2, b8, b9, b10, b11, c2, c3, c7, c8, c9, c10, d2, d3, d4, d7, e1, e2 vdda +1.8 v analog supply voltage input. g12, g13, g14, h11, h12, h13, h14, j3, j4, j11, j12, j13, j14 vdd +1.8 v digital supply voltage input. c13, c14, d12, d13, d14, e11, e12, e13, e14, f11, f12, f13, f14, g1, g2, g3, g11, h3, h4 vss +1.8 v digital supply return.
data sheet ad9119/ad9129 rev. 0 | page 11 of 68 pin no. mn emonic description a12, a13, a14, b12, b13, c11, c12, d5, d6, d8, d9, d10, d11, e3, e4, f1, f2, f3, f4, g4 vssc analog supply return. a6 ioutp dac positive current output source. a7 ioutn dac negative current output source. b14 sync synchronization signal output. c1, d1 dacclk_n, dacclk_p negative/positive dac clock input. h1 reset reset input. active high. if unused, ti e this pin to vss. h2 irq interrupt request open - drain output. active high. pull up this pin to vdd with a 1 k? resistor. j1 sdio serial port data input/output. j2 sdo serial port data output. k1 sclk serial port clock input. k2 cs serial port enable input. k3, k4 dci_p, dci_n positive, negative data clock input (dci). k11, k12 d c o _ p, dc o_n positive, negative data clock output (dco). k13, k14 frm_p, frm_n positive, negative data frame/parity signal (frame/parity). l1, m1 p1_d0p, p1_d0n data port 1 positive/negative data input bit 0. l2, m2 p1_d1p, p1_d1n data port 1 positive/negativ e data input bit 1. l3, m3 p1_d2p, p1_d2n data port 1 positive/negative data input bit 2. l4, m4 p1_d3p, p1_d3n data port 1 positive/negative data input bit 3. l5, m5 p1_d4p, p1_d4n data port 1 positive/negative data input bit 4. l6, m6 p1_d5p, p1_ d5n data port 1 positive/negative data input bit 5. l7, m7 p1_d6p, p1_d6n data port 1 positive/negative data input bit 6. l8, m8 p1_d7p, p1_d7n data port 1 positive/negative data input bit 7. l9, m9 p1_d8p, p1_d8n data port 1 positive/negative data i nput bit 8. l10, m10 p1_d9p, p1_d9n data port 1 positive/negative data input bit 9. l11, m11 p1_d10p, p1_d10n data port 1 positive/negative data input bit 10. l12,m12 p1_d11p, p1_d11n data port 1 positive/negative data input bit 11. l13, m13 p1_d12p , p1_d12n data port 1 positive/negative data input bit 12. l14, m14 p1_d13p, p1_d13n data port 1 positive/negative data input bit 13. n1, p1 p0_d0p, p0_d0n data port 0 positive/negative data input bit 0. n2, p2 p0_d1p, p0_d1n data port 0 positive/neg ative data input bit 1. n3, p3 p0_d2p, p0_d2n data port 0 positive/negative data input bit 2. n4, p4 p0_d3p, p0_d3n data port 0 positive/negative data input bit 3. n5, p5 p0_d4p, p0_d4n data port 0 positive/negative data input bit 4. n6, p6 p0_d5p, p0_d5n data port 0 positive/negative data input bit 5. n7, p7 p0_d6p, p0_d6n data port 0 positive/negative data input bit 6. n8, p8 p0_d7p, p0_d7n data port 0 positive/negative data input bit 7. n9, p9 p0_d8p, p0_d8n data port 0 positive/negative da ta input bit 8. n10, p10 p0_d9p, p0_d9n data port 0 positive/negative data input bit 9. n11, p11 p0_d10p, p0_d10n data port 0 positive/negative data input bit 10. n12, p12 p0_d11p, p0_d11n data port 0 positive/negative data input bit 11. n13, p13 p 0_d12p, p0_d12n data port 0 positive/negative data input bit 12. n14, p14 p0_d13p, p0_d13n data port 0 positive/negative data input bit 13.
ad9119/ad9129 data sheet rev. 0 | page 12 of 68 typical performance characteristics ad9119 static linearity i outfs = 28 ma, nominal supplies, t a = 25c, unless otherwise noted. code in l (lsb) ?0.2 ?0.1 0 0.1 0.2 0.3 0 200 400 600 800 1000 1200 1400 1600 1800 2000 11 149-004 figure 4 . typical inl, 11 ma at 25c in l (lsb) ?0.2 ?0.1 0 0.1 0.2 0.3 code 0 200 400 600 800 1000 1200 1400 1600 1800 2000 11 149-005 figure 5 . typical inl, 22 ma at 25c in l (lsb) ?0.2 ?0.1 0 0.1 0.2 0.3 code 0 200 400 600 800 1000 1200 1400 1600 1800 2000 11 149-006 figure 6 . typical inl, 33 ma at 25c ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 code dn l (lsb) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 11 149-007 figure 7 . typical dnl, 11 ma at 25c ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 code dn l (lsb) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 11 149-008 figure 8 . typical dnl, 22 ma at 25c ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 code dn l (lsb) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 11 149-009 figure 9 . typical dnl, 33 ma at 25c
data sheet ad9119/ad9129 rev. 0 | page 13 of 68 ac (normal mode) i outfs = 28 ma, f dac = 2.6 gsp s, nominal supplies, t a = 25c, unless otherwise noted. ?95 st art 20mhz res bw 20khz vbw 20khz sweep 7.78s (1001 pts) ref 5dbm 10db/div stop 2.6ghz ?85 ?75 ?65 ?55 ?45 ?35 ?25 ?5 ?15 5 11 149-0 11 figure 10 . single - tone spectrum at f out = 70 mhz 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0 200 400 600 800 1000 1200 1400 sfdr (dbc) f out (mhz) 1400msps 1600msps 2200msps 2600msps 2800msps 11 149-013 figure 11 . sfdr vs. f out over f dac ?145 ?150 ?155 ?160 ?165 ?170 0 200 400 600 800 1000 1200 1400 nsd (dbm/hz) f out (mhz) 1600msps 2200msps 2800msps 11 149-015 figure 12 . single - tone nsd vs . f out ?95 st art 20mhz res bw 20khz vbw 20khz sweep 7.78s (1001 pts) ref 5dbm stop 2.6ghz ?85 ?75 ?65 ?55 ?45 ?35 ?25 ?5 ?15 5 11 149-012 10db/div figure 13 . single - tone spectrum at f out = 1000 mhz ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 0 200 400 600 800 1000 1200 1400 imd (dbc) f out (mhz) 1600msps 2200msps 2600msps 2800msps 11 149-014 figure 14 . imd vs. f out over f dac ?150 ?155 ?160 ?165 ?170 0 200 400 600 800 1000 1200 nsd (dbm/hz) f out (mhz) 1600msps 2200msps 2800msps 11 149-016 figure 15 . w- cdma nsd vs. f out
ad9119/ad9129 data sheet rev. 0 | page 14 of 68 i outfs = 28 ma, f dac = 2.6 gsps, nominal s upplies, t a = 25c, unless otherwise noted. ?45 ?50 ?55 ?60 ?65 ?70 ?75 ?80 0 200 400 600 800 1000 1200 1400 sfdr (dbc) f out (mhz) ?16dbfs ?12dbfs ?6dbfs 0dbfs 11 149-017 figure 16 . sfdr vs. f out over digital full scale ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 200 400 600 800 1000 1200 1400 imd (dbc) f out (mhz) ?16dbfs ?12dbfs ?6dbfs 0dbfs 11 149-020 figure 17 . imd vs. f out over digital full scale ?30 ?40 ?50 ?60 ?70 ?80 ?90 0 200 400 600 800 1000 1200 1400 sfdr (dbc) f out (mhz) 11ma 22ma 33ma 11 149-021 figure 18 . sfdr vs. f out ove r dac i outfs 0 200 400 600 800 1000 1200 1400 f out (mhz) 11ma 22ma 33ma ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 imd (dbc) 11 149-022 figure 19 . imd vs. f out over dac i outfs
data sheet ad9119/ad9129 rev. 0 | page 15 of 68 i outfs = 28 ma, f dac = 2.6 gsps, nominal supplies, t a = 25c, unless otherwise noted. 0 200 400 600 800 1000 1200 1400 nsd (dbm/hz) f out (mhz) ?145 ?150 ?155 ?160 ?165 ?170 ?40c +25c +85c 11 149-025 figure 20 . single - tone nsd vs. f out over temperature center 877.5mhz vbw 3khz nsd (dbm/hz) sp an 53.84mhz sweep 1.485s ?20 ?30 ?50 ?40 ?80 ?70 ?60 ?90 ?120 ?1 10 ?100 offset freq 5mhz 10mhz 15mhz 20mhz 25mhz integ bw 3.84mhz 3.84mhz 3.84mhz 3.84mhz 3.84mhz dbc ?74.97 ?77.99 ?78.68 ?78.79 ?76.81 dbm ?85.68 ?88.69 ?89.38 ?89.50 ?87.52 dbc ?75.24 ?78.44 ?78.94 ?78.58 ?77.20 dbm ?85.95 ?89.14 ?89.65 ?89.29 ?87.91 fi l ter off off off off off total carrier power ?10.705dbm/3.84mhz upper lower 11 149-027 figure 21 . single - carrier w- cdma at 877.5 mhz 0 200 400 600 800 1000 1200 f out (mhz) nsd (dbm/hz) ?150 ?155 ?160 ?165 ?170 ?40c +25c +85c 11 149-026 figure 22 . w- cdma nsd vs. f out over temperature center 877.5mhz vbw 3khz nsd (dbm/hz) sp an 58.84mhz sweep 1.623s ?20 ?30 ?50 ?40 ?80 ?70 ?60 ?90 ?120 ?1 10 ?100 offset freq 5mhz 10mhz 15mhz 20mhz 25mhz integ bw 3.84mhz 3.84mhz 3.84mhz 3.84mhz 3.84mhz dbc ?71.62 ?74.36 ?74.35 ?72.89 ?67.34 dbm ?85.23 ?87.96 ?87.95 ?86.50 ?80.95 dbc ?71.61 ?74.94 ?74.91 ?74.53 ?73.68 dbm ?85.22 ?88.55 ?88.52 ?88.14 ?87.29 fi l ter off off off off off upper lower total carrier power ?10.646dbm/7.68mhz 11 149-028 figure 23 . two - carrier w- cdma at 87 7. 5 mhz
ad9119/ad9129 data sheet rev. 0 | page 16 of 68 ac (mix - mode) i outfs = 28 ma, f dac = 2.6 gsps, nominal supplies, t a = 25c, unless otherwise noted. ?100 st art 20mhz res bw 20khz vbw 20khz sweep 7.78s (1001 pts) ref 0dbm 10db/div stop 2.6ghz ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?10 ?20 0 11 149-029 figure 24 . single tone spectrum at f out = 2350 mhz 500 1000 1500 2000 2500 3000 sfdr (dbc) f out (mhz) 1600msps 2200msps 2800msps ?40 ?50 ?60 ?70 ?80 ?90 11 149-031 figure 25 . sfdr vs. f out over f dac 1000 1500 2000 3500 3500 2500 4000 4500 nsd (dbm/hz) f out (mhz) ?145 ?150 ?155 ?160 ?165 ?170 11 149-033 figure 26 . s ingle - tone nsd vs. f out ?95 st art 20mhz res bw 20khz vbw 20khz sweep 7.78s (1001 pts) ref 5dbm stop 2.6ghz ?85 ?75 ?65 ?55 ?45 ?35 ?25 ?5 ?15 5 11 149-030 10db/div figure 27 . single - tone spectrum at f out = 1600 mhz 500 1000 1500 2000 2500 3000 f out (mhz) 1600msps 2200msps 2800msps imd (dbc) ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 11 149-032 figure 28 . imd vs. f out over f dac 1500 2000 2500 3000 3500 4000 f out (mhz) nsd (dbm/hz) ?145 ?150 ?155 ?160 ?165 ?170 11 149-034 figure 29 . w- cdma nsd vs. f out
data sheet ad9119/ad9129 rev. 0 | page 17 of 68 i outfs = 28 ma, f dac = 2. 6 gsps, nominal supplies, t a = 25c, unless otherwise noted. 1000 1500 2000 2500 3000 3500 4000 f out (mhz) sfdr (dbc) ?25 ?55 ?60 ?45 ?50 ?35 ?40 ?30 ?65 ?70 11 149-035 second nyquist zone third nyquist zone ?16dbfs ?12dbfs ?6dbfs 0dbfs figure 30 . sfdr vs. f out over digital full scale 1000 1500 2000 2500 3000 3500 4000 f out (mhz) imd (dbc) ?45 ?65 ?70 ?55 ?60 ?50 ?75 ?80 11 149-036 second nyquist zone third nyquist zone ?16dbfs ?12dbfs ?6dbfs 0dbfs figure 31 . imd vs. f out over digital full scale 1000 1500 2000 3500 3500 2500 4000 f out (mhz) sfdr (dbc) ?25 ?55 ?60 ?45 ?50 ?35 ?40 ?30 ?65 ?70 11 149-039 second nyquist zone third nyquist zone 1 1m a 22m a 33m a figure 32 . sfdr vs. f out over dac i outfs 1000 1500 2500 2000 3000 3500 4000 f out (mhz) imd (dbc) ?45 ?50 ?55 ?60 ?65 ?80 ?75 ?70 11 149-040 second nyquist zone third nyquist zone 1 1m a 22m a 33m a figure 33 . imd vs. f out over dac i outfs
ad9119/ad9129 data sheet rev. 0 | page 18 of 68 i outfs = 28 ma, f dac = 2.6 gsps, nominal supplies, t a = 25c, unless otherwise noted. 1000 1500 2000 3500 3500 2500 4000 f out (mhz) ?145 nsd (dbm/hz) ?150 ?155 ?160 ?165 ?170 11 149-043 ?40c +25c +85c figure 34 . single - tone nsd vs. f out o ver temperature center 1.888ghz vbw 3khz nsd (dbm/hz) sp an 53.84mhz sweep 1.485s ?20 ?30 ?50 ?40 ?80 ?70 ?60 ?90 ?120 ?1 10 ?100 offset freq 5mhz 10mhz 15mhz 20mhz 25mhz integ bw 3.84mhz 3.84mhz 3.84mhz 3.84mhz 3.84mhz dbc ?70.25 ?74.47 ?75.55 ?76.03 ?76.62 dbm ?80.37 ?84.60 ?85.68 ?86.15 ?86.75 dbc ?70.38 ?74.54 ?75.72 ?76.25 ?76.70 dbm ?80. 50 ?84. 66 ?85.85 ?86.37 ?86.83 fi l ter off off off off off total carrier power ?10.125dbm/3.84mhz upper lower 11 149-045 figure 35 . single - carrier w- cdma at 1887.5 mhz 1500 2500 2000 3000 3500 3500 f out (mhz) nsd (dbm/hz) ?145 ?150 ?155 ?160 ?165 11 149-044 ?40c +25c +85c figure 36 . w- cdma nsd vs. f out over temperature center 1.98ghz vbw 3khz nsd (dbm/hz) sp an 58.84mhz sweep 1.623s ?20 ?30 ?50 ?40 ?80 ?70 ?60 ?90 ?120 ?1 10 ?100 offset freq 5mhz 10mhz 15mhz 20mhz integ bw 3.84mhz 3.84mhz 3.84mhz 3.84mhz dbc ?65.84 ?67.02 ?68.05 ?69.07 dbm ?82.06 ?83.23 ?84.27 ?85.29 dbc ?65.79 ?66.75 ?67.99 ?69.03 dbm ?82.01 ?82.97 ?84.21 ?85.25 fi l ter off off off off upper lower total carrier power ?10.251dbm/15.36mhz 11 149-046 figure 37 . four - carrier w- cdma at 1980 mhz
data sheet ad9119/ad9129 rev. 0 | page 19 of 68 docsis per formance (normal mode) i outfs = 33 ma, f dac = 2.782 gsps, nominal supplies, t a = 25c, unless otherwise noted. ?120 st art 0hz res bw 20khz vbw 2khz sweep 27.9s (1001 pts) ref ?20dbm 10db/div stop 1.1ghz ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?30 ?40 ?20 y ?3.819dbm () C74.107db () C74.148db x 70mhz () 70mhz () 140mhz function v alue ?3.819dbm () C74.24db () C74.17db function width 6mhz 6mhz 6mhz function band power band power band power mode n 1 1 trc 1 1 1 sc l f f f 1 21 31 11 149-049 figure 38 . single carrier at 70 mhz output ?120 st art 0hz res bw 20khz vbw 2khz sweep 27.9s (1001 pts) ref ?20dbm stop 1.1ghz ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?30 ?40 ?20 y ?12.143dbm () C70.38db () C67.78db x 79mhz () 61mhz () 131mhz function v alue ?12.142dbm () C70.351db () C67.775db function width 6mhz 6mhz 6mhz function band power band power band power mode n 1 1 trc 1 1 1 sc l f f f 1 21 31 11 149-050 10db/div figure 39 . four carrier at 70 mhz output ?120 st art 0hz res bw 20khz vbw 20khz sweep 27.9s (1001 pts) ref ?20dbm stop 1.1ghz ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?30 ?40 ?20 y ?15.295dbm () C66.768db () C66.821db x 91mhz () 49mhz () 1 17.9mhz function v alue ?15.294dbm () C66.669db () C66.833db function width 6mhz 6mhz 6mhz function band power band power band power mode n 1 1 trc 1 1 1 sc l f f f 21 31 1 11 149-051 10db/div figure 40 . eight carrier at 70 mhz output ?120 st art 0hz res bw 20khz vbw 2khz sweep 27.9s (1001 pts) ref ?20dbm stop 1.1ghz ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?30 ?40 ?20 y ?6.351dbm () C66.696db () C70.598db x 950mhz () C68mhz () C882mhz function v alue ?6.349dbm () C66.696db () C70.598db function width 6mhz 6mhz 6mhz function band power band power band power mode n 1 1 trc 1 1 1 sc l f f f 1 21 31 11 149-052 10db/div figure 41 . single carrier at 950 mhz output ?120 st art 0hz res bw 20khz vbw 2khz sweep 27.9s (1001 pts) ref ?20dbm stop 1.1ghz ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?30 ?40 ?20 y ?14.282dbm () C64.535db () C68.529db x 959mhz () C77mhz () C891mhz function v alue ?14.264dbm () C64.535db () C68.597db function width 6mhz 6mhz 6mhz function band power band power band power mode n 1 1 trc 1 1 1 sc l f f f 21 31 1 11 149-053 10db/div figure 42 . four carrier at 950 mhz output ?120 st art 0hz res bw 20khz vbw 2khz sweep 27.9s (1001 pts) ref ?20dbm stop 1.1ghz ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?30 ?40 ?20 y ?14.632dbm () C62.657db () C66.131db x 971mhz () C89mhz () C903mhz function v alue ?18.397dbm () C62.657db () C66.195db function width 6mhz 6mhz 6mhz function band power band power band power mode n 1 1 trc 1 1 1 sc l f f f 1 21 31 11 149-054 10db/div figure 43 . eigh t carrier at 950 mhz output
ad9119/ad9129 data sheet rev. 0 | page 20 of 68 i outfs = 33 ma, f dac = 2.782 gsps, nominal supplies, t a = 25c, unless otherwise noted. 0 0.2 0.4 0.8 0.6 1.0 f out (ghz) in-band second harmonic (dbc) ?40 ?50 ?80 ?70 ?60 ?90 11 149-055 figure 44 . second harmonic vs. f out performance for one docsis c arrier 0 0.2 0.4 0.8 0.6 1.0 f out (ghz) in-band second harmonic (dbc) ?40 ?50 ?80 ?70 ?60 ?90 11 149-056 figure 45 . second harmonic vs. f out performance for four docsis carriers 0 0.2 0.4 0.8 0.6 1.0 f out (ghz) in-band second harmonic (dbc) ?40 ?80 ?70 ?60 ?50 ?90 11 149-057 figure 46 . second harmonic vs. f out performance for eight docsis carriers 0 0.2 0.4 0.8 0.6 1.0 f out (ghz) in-band third harmonic (dbc) ?40 ?80 ?70 ?60 ?50 ?90 11 149-058 figure 47 . third harmonic vs. f out performance for one docs is c arrier 0 0.2 0.4 0.8 0.6 1.0 f out (ghz) in-band third harmonic (dbc) ?40 ?80 ?70 ?60 ?50 ?90 11 149-059 figure 48 . third harmonic vs. f out performance for four docsis carriers 0 0.2 0.4 0.8 0.6 1.0 f out (ghz) in-band third harmonic (dbc) ?40 ?80 ?70 ?60 ?50 ?90 11 149-060 figure 49 . third harmonic vs. f out performance for eight docsis carriers
data sheet ad9119/ad9129 rev. 0 | page 21 of 68 i outfs = 33 ma, f dac = 2.782 gsps, no minal supplies, t a = 25c, unless otherwise noted. 0 0.2 0.4 0.8 0.6 1.0 f out (ghz) acpr (dbc) ?50 ?55 ?65 ?80 ?70 ?75 ?85 ?60 ?90 11 149-167 acp1 acp2 acp3 acp4 acp5 figure 50 . single - carrier acp r vs. f out 0 0.2 0.4 0.8 0.6 1.0 f out (ghz) acpr (dbc) ?50 ?55 ?65 ?80 ?70 ?75 ?85 ?60 ?90 11 149-168 acp1 acp2 acp3 acp4 acp5 figure 51 . four - carrier acpr vs. f out 0 0.2 0.4 0.8 0.6 1.0 f out (ghz) acpr (dbc) ?50 ?75 ?80 ?65 ?70 ?60 ?55 ?85 ?90 11 149-169 acp1 acp2 acp3 acp4 acp5 figure 52 . eight - carrier acpr vs. f out 0 0.2 0.4 0.8 0.6 1.0 f out (ghz) acpr (dbc) ?50 ?75 ?80 ?65 ?70 ?60 ?55 ?85 ?90 11 149-170 acp1 acp2 acp3 acp4 acp5 figure 53 . 16 - carrier acpr vs. f out 0.1 0.2 0.4 0.3 0.5 0.7 0.8 0.6 0.9 f out (mhz) acpr (dbc) ?50 ?75 ?80 ?65 ?70 ?60 ?55 ?85 ?90 11 149-171 acp1 acp2 acp3 acp4 acp5 figure 54 . 32 - carrier acpr vs. f out ?120 center 77mhz res bw 10khz vbw 1khz sweep 6.08s (1001 pts) ref ?20dbm sp an 60mhz ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?30 ?40 ?20 11 149-172 10db/div figure 55 . gap channel acpr at 77 mhz
ad9119/ad9129 data sheet rev. 0 | page 22 of 68 ad9129 static linearity i outfs = 28 ma, nominal supplies, t a = 25c, unless otherwise noted. ?1.5 ?1.0 ?0.5 0 in l (lsb) 0.5 1.0 1.5 2.0 0 2000 4000 6000 8000 code 10000 12000 14000 16000 11 149-065 figure 56 . typical inl, 11 ma at 25c ?1.5 ?1.0 ?0.5 0 in l (lsb) 0.5 1.0 1.5 2.0 0 2000 4000 6000 8000 code 10000 12000 14000 16000 11 149-066 figure 57 . typical inl, 22 ma at 25c 0 2000 4000 6000 8000 code 10000 12000 14000 16000 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 in l (lsb) 11 149-067 figure 58 . typical inl, 33 ma at 25c code 0 2000 4000 6000 8000 10000 12000 14000 16000 ?1.5 ?1.0 ?0.5 0 0.5 1. 0 dn l (lsb) 11 149-068 figure 59 . typical dnl, 11 ma at 25c code 0 2000 4000 6000 8000 10000 12000 14000 16000 dn l (lsb) ?1.5 ?1.0 ?0.5 0 0.5 1.0 11 149-069 figure 60 . typical dnl, 22 ma at 25c code 0 2000 4000 6000 8000 10000 12000 14000 16000 ?1.5 ?1.0 ?0.5 0 0.5 1.0 dn l (lsb) 11 149-070 figure 61 . typical dnl, 33 ma at 25c
data sheet ad9119/ad9129 rev. 0 | page 23 of 68 ac (normal mode) i outfs = 28 ma, f dac = 2.6 gsps, nominal supplies, t a = 25c, unless otherwise noted. ?95 st art 20mhz res bw 20khz ref 5dbm stop 2.6ghz ?85 ?75 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 11 149-071 vbw 20khz sweep 7.78s (1001 pts) 10db/div figure 62 . single - tone spectrum at f out = 70 mhz 0 200 400 600 800 f out (mhz) sfdr (dbc) 1000 1200 1400 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 1400msps 1600msps 2200msps 2600msps 2800msps 11 149-073 figure 63 . sfdr vs. f out over f dac 0 200 400 600 800 f out (mhz) nsd (dbm/hz) 1000 1200 1400 ?145 ?150 ?155 ?160 ?165 ?170 1600msps 2200msps 2800msps 11 149-075 figure 64 . single - tone nsd vs. f out ?95 st art 20mhz res bw 20khz ref 5dbm stop 2.6ghz ?85 ?75 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 11 149-072 vbw 20khz sweep 7.78s (1001 pts) 10db/div figure 65 . single - tone spectrum at f out = 1000 mhz 0 200 400 600 800 f out (mhz) imd (dbc) 1000 1200 1400 ?40 ?50 ?60 ?70 ?80 ?90 ?100 1600msps 2200msps 2600msps 2800msps 11 149-074 figure 66 . imd vs. f out over f dac 0 200 400 600 800 f out (mhz) nsd (dbm/hz) 1000 1200 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 11 149-076 1600msps 2200msps 2800msps figure 67 . w- cdma nsd vs. f out
ad9119/ad9129 data sheet rev. 0 | page 24 of 68 i outfs = 28 ma , f dac = 2.6 gsps, nominal supplies, t a = 25c, unless otherwise noted. 0 200 400 600 800 f out (mhz) sfdr (dbc) 1000 1400 1200 ?45 ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?16dbfs ?12dbfs ?6dbfs 0dbfs 11 149-077 figure 68 . sfdr vs. f out over digital full scale 0 200 400 600 800 f out (mhz) in-band second harmonic (dbc) 1000 1400 1200 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?16dbfs ?12dbfs ?6dbfs 0dbfs 11 149-078 figure 69 . sfdr for second harmonic vs. f out over digital full scale ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 200 400 600 800 f out (mhz) in-band third harmonic (dbc) 1000 1400 1200 ?16dbfs ?12dbfs ?6dbfs 0dbfs 11 149-079 figu re 70 . sfdr for third harmonic vs. f out over digital full scale 0 200 400 600 800 f out (mhz) imd (dbc) 1000 1400 1200 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?16dbfs ?12dbfs ?6dbfs 0dbfs 11 149-080 figure 71 . imd vs. f out over digital full scale 0 200 400 600 800 f out (mhz) sfdr (dbc) 1000 1400 1200 ?30 ?40 ?50 ?60 ?70 ?80 ?90 11ma 22ma 33ma 11 149-081 figure 72 . sfdr vs. f out over dac i outfs 0 200 400 600 800 f out (mhz) imd (dbc) 1000 1400 1200 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 11ma 22ma 33ma 11 149-082 figure 73 . imd vs. f out over dac i outfs
data sheet ad9119/ad9129 rev. 0 | page 25 of 68 i outfs = 28 ma, f dac = 2.6 gsps, nominal supplies, t a = 25c, unless otherwise noted. 0 200 400 600 800 f out (mhz) sfdr (dbc) 1000 1400 1200 ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?40c +25c +85c 11 149-083 figure 74 . sfdr vs. f out over temperature 0 200 400 600 800 f out (mhz) imd (dbc) 1000 1400 1200 ?60 ?65 ?70 ?75 ?80 ?85 ?40c +25c +85c 11 149-084 figure 75 . imd vs. f out over temperature center 877.5mhz vbw 3khz nsd (dbm/hz) sp an 53.84mhz sweep 1.485s ?20 ?30 ?50 ?40 ?80 ?70 ?60 ?90 ?120 ?1 10 ?100 offset freq 5mhz 10mhz 15mhz 20mhz 25mhz integ bw 3.84mhz 3.84mhz 3.84mhz 3.84mhz 3.84mhz dbc ?76.29 ?80.60 ?81.37 ?81.76 ?79.29 dbm ?87.08 ?91.39 ?92.16 ?92.56 ?90.08 dbc ?75.85 ?79.88 ?81.09 ?81.89 ?80.89 dbm ?86.64 ?90.68 ?91.89 ?92.68 ?91.69 fi l ter off off off off off total carrier power ?10.794dbm/3.84mhz 11 149-087 figure 76 . single - carrier w- cdma at 877.5 mhz 0 200 400 600 800 f out (mhz) nsd (dbm/hz) 1000 1200 ?150 ?155 ?160 ?165 ?170 ?40c +25c +85c 11 149-086 figure 77 . w- cdma nsd vs. f out over temperature 0 200 400 600 800 f out (mhz) nsd (dbm/hz) 1000 1400 1200 ?145 ?150 ?155 ?160 ?165 ?170 ?40c +25c +85c 11 149-085 figure 78 . single - tone nsd vs. f out over temperature center 877.5mhz vbw 3khz nsd (dbm/hz) sp an 58.84mhz sweep 1.623s ?20 ?30 ?50 ?40 ?80 ?70 ?60 ?90 ?120 ?1 10 ?100 offset freq 5mhz 10mhz 15mhz 20mhz 25mhz integ bw 3.84mhz 3.84mhz 3.84mhz 3.84mhz 3.84mhz dbc ?72.33 ?75.18 ?74.76 ?72.69 ?65.42 dbm ?85.89 ?88.74 ?88.32 ?86.25 ?78.99 dbc ?72.37 ?75.19 ?74.92 ?74.60 ?73.53 dbm ?85.93 ?88.75 ?88.48 ?88.16 ?87.09 fi l ter off off off off off total carrier power ?10.599dbm/7.68mhz 11 149-088 figure 79 . two - carrier w- cdma at 875 mhz
ad9119/ad9129 data sheet rev. 0 | page 26 of 68 i outfs = 28 ma, f dac = 2.6 gsps, nominal supplies, t a = 25c, unless otherwise noted. 700 750 800 850 900 f out (mhz) aclr (dbc) 950 1000 ?60 ?75 ?70 ?65 ?80 ?85 ?90 first aclr (dbc) second aclr (dbc) 11 149-089 figure 80 . single - carrier w- cdma aclr vs. f out (first aclr, second aclr ) f out (mhz) aclr (dbc) ?60 ?75 ?70 ?65 ?80 ?85 ?90 11 149-090 third aclr (dbc) fourth aclr (dbc) fifth aclr (dbc) 700 750 800 850 900 950 1000 figure 81 . single - carrier w- cdma aclr vs. f out ( third aclr , fourth aclr, fifth aclr ) f out (mhz) aclr (dbc) ?60 ?75 ?70 ?65 ?80 ?85 ?90 11 149-091 first aclr (dbc) second aclr (dbc) 700 750 800 850 900 950 figure 82 . two - carrier w- cdma aclr vs. f out (first aclr, second aclr) f out (mhz) aclr (dbc) ?60 ?75 ?70 ?65 ?80 ?85 ?90 11 149-092 third aclr (dbc) fourth aclr (dbc) fifth aclr (dbc) 700 750 800 850 900 950 figure 83 . two - carrier w- cdma aclr vs. f out ( third aclr, fourth aclr, fifth aclr)
data sheet ad9119/ad9129 rev. 0 | page 27 of 68 ac (mix - mode) i outfs = 28 ma, f dac = 2.6 gsps, nominal supplies, t a = 25c, unless otherwise noted. ?90 st art 20mhz res bw 20khz vbw 20khz sweep 7.78s (1001 pts) ref 0dbm stop 2.6ghz ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 11 149-093 10db/div figure 84 . single - tone spectrum at f out = 2350 mh z ?90 500 1500 1000 2000 2500 f out (mhz) sfdr (dbm) 3000 ?70 ?80 ?50 ?60 ?40 1600 2200 2800 11 149-095 figure 85 . sfdr vs. f out over f dac ?170 1000 2000 1500 2500 3500 4000 3000 f out (mhz) nsd (dbm/hz) 4500 ?160 ?165 ?150 ?155 ?145 11 149-097 figure 86 . single - tone nsd vs. f out ?95 st art 20mhz res bw 20khz vbw 20khz sweep 7.78s (1001 pts) ref 5dbm stop 2.6ghz ?85 ?75 ?65 ?55 ?45 ?35 ?25 ?5 ?15 5 11 149-094 10db/div figure 87 . single - tone spectrum at f out = 1600 mhz ?85 500 1500 1000 2000 2500 f out (mhz) imd (dbc) 3000 ?65 ?70 ?80 ?75 ?60 ?55 ?50 1600msps 2200msps 2800msps 11 149-096 figure 88 . imd v s. f out over f dac ?170 1500 2500 2000 3000 3500 f out (mhz) nsd (dbm/hz) 4000 ?160 ?165 ?150 ?155 ?145 11 149-098 figure 89 . w- cdma nsd vs. f out
ad9119/ad9129 data sheet rev. 0 | page 28 of 68 i outfs = 28 ma, f dac = 2.6 gsps, nominal supplies, t a = 25c, unless otherwise noted. ?70 1000 2000 1500 2500 3500 f out (mhz) sfdr (dbm) 4000 3000 ?50 ?55 ?65 ?60 ?45 ?40 ?35 ?30 ?25 second nyquist zone third nyquist zone ?16dbfs ?12dbfs ?6dbfs 0dbfs 11 149-099 figure 90 . sfdr vs. f out over digital full scale ?80 1000 2000 1500 2500 3500 3000 f out (mhz) imd (dbc) 4000 ?60 ?65 ?70 ?75 ?50 ?55 ?45 second nyquist zone third nyquist zone ?16dbfs ?12dbfs ?6dbfs 0dbfs 11 149-100 figure 91 . imd vs. f out over digital full scale ?90 1000 1500 2500 2000 3000 3500 f out (mhz) sfdr (dbm) 4000 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 0 second nyquist zone third nyquist zone 11ma 22ma 33ma 11 149-101 figure 92 . sfdr vs. f out over dac i outfs ?90 1000 2000 1500 2500 3500 3000 f out (mhz) imd (dbc) 4000 ?60 ?70 ?80 ?50 ?40 ?30 11 149-193 second nyquist zone third nyquist zone 11ma 22ma 33ma figure 93 . imd vs. f out over dac i outfs
data sheet ad9119/ad9129 rev. 0 | page 29 of 68 i outfs = 28 ma, f dac = 2.6 gsps, nominal suppl ies, t a = 25c, unless otherwise noted. ?170 1000 2000 1500 2500 3500 3000 f out (mhz) nsd (dbm/hz) 4000 ?160 ?165 ?150 ?155 ?145 11 149-105 ?40c +25c +85c figure 94 . single - tone nsd vs. f out over temperature center 1.888ghz vbw 3khz nsd (dbm/hz) sp an 53.84mhz sweep 1.485s ?20 ?30 ?50 ?40 ?80 ?70 ?60 ?90 ?120 ?1 10 ?100 offset freq 5mhz 10mhz 15mhz 20mhz 25mhz integ bw 3.84mhz 3.84mhz 3.84mhz 3.84mhz 3.84mhz dbc ?73.71 ?77.40 ?78.04 ?78.13 ?78.01 dbm ?83.15 ?86.84 ?87.48 ?87.57 ?87.46 dbc ?74.00 ?77.31 ?77.85 ?78.51 ?78.43 dbm ?83.45 ?86.75 ?87.30 ?87.96 ?87.87 fi l ter off off off off off total carrier power ?9.445dbm/3.84mhz 11 149-107 upper lower figure 95 . single - carrier w- cdma at 1887.5 mhz ?165 1500 2500 2000 3000 3500 f out (mhz) nsd (dbm/hz) ?150 ?155 ?160 ?145 ?40c +25c +85c 11 149-106 figure 96 . w- cdma nsd vs. f ou t over temperature center 1.98ghz vbw 3khz nsd (dbm/hz) sp an 58.84mhz sweep 1.623s ?20 ?30 ?50 ?40 ?80 ?70 ?60 ?90 ?120 ?1 10 ?100 offset freq 5mhz 10mhz 15mhz 20mhz integ bw 3.84mhz 3.84mhz 3.84mhz 3.84mhz dbc ?69.05 ?69.86 ?70.81 ?71.03 dbm ?85.24 ?86.05 ?87.00 ?87.22 dbc ?69.03 ?69.71 ?70.52 ?70.91 dbm ?85.22 ?85.90 ?86.71 ?87.10 fi l ter off off off off upper lower total carrier power ?10.2 1 1dbm/15.36mhz 11 149-108 figure 97 . four - carrier w- cdma at 1980 mhz
ad9119/ad9129 data sheet rev. 0 | page 30 of 68 i outfs = 28 ma, f dac = 2.6 gsps, nominal supplies, t a = 25c, unless otherwise noted. 1.4 1.6 1.8 2.0 2.2 f out (ghz) aclr (dbc) 2.4 2.6 ?50 ?60 ?75 ?70 ?55 ?65 ?80 ?85 ?90 first aclr (dbc) second aclr (dbc) 11 149-109 figure 98 . single - carrier w- cdma aclr vs. f out (first aclr, second aclr) 1.4 1.6 1.8 2.0 2.2 f out (ghz) aclr (dbc) 2.4 2.6 ?50 ?60 ?75 ?70 ?55 ?65 ?80 ?85 ?90 11 149- 1 10 third aclr (dbc) fourth aclr (dbc) fifth aclr (dbc) figure 99 . single - carrier w- cdma aclr vs. f out (third aclr, fourth aclr, fifth aclr) 1.4 1.6 1.8 2.0 2.2 f out (ghz) aclr (dbc) 2.4 2.6 ?50 ?60 ?75 ?70 ?55 ?65 ?80 ?85 ?90 first aclr (dbc) second aclr (dbc) 11 149- 11 1 figure 100 . four - carrier w- cdma aclr vs. f out (first aclr, second aclr) 1.4 1.6 1.8 2.0 2.2 f out (ghz) aclr (dbc) 2.4 2.6 ?50 ?60 ?75 ?70 ?55 ?65 ?80 ?85 ?90 11 149- 1 12 third aclr (dbc) fourth aclr (dbc) fifth aclr (dbc) figure 101 . four - carrier w- cdma aclr vs. f out (third aclr, fourth aclr, fifth aclr)
data sheet ad9119/ad9129 rev. 0 | page 31 of 68 docsis performance (normal mode) i outfs = 33 ma, f dac = 2.782 gsps, nominal supplies, t a = 25c, unless otherwise noted. ?120 st art 0hz res bw 20khz vbw 20khz sweep 27.9s (1001 pts) ref ?20dbm stop 1.1ghz ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?30 ?40 ?20 y ?3.6 1 1dbm () C72.929db () C74.629db x 70mhz () 70mhz () 140mhz function v alue ?3.612dbm () C72.903db () C74.583db function width 6mhz 6mhz 6mhz function band power band power band power mode n 1 1 trc 1 1 1 sc l f f () f () 21 1 31 11 149- 1 13 10db/div figure 102 . single carrier at 70 mhz output ?120 ?20 st art 0hz res bw 20khz vbw 20khz sweep 27.9s (1001 pts) ref ?20dbm stop 1.1ghz ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?30 ?40 y ?1 1.506dbm () C71.473db () C69.109db x 79mhz () 61mhz () 131mhz function v alue ?1 1.506dbm () C71.606db () C69.155db function width 6mhz 6mhz 6mhz function band power band power band power mode n 1 1 trc 1 1 1 sc l f f () f () 21 1 31 11 149- 1 14 10db/div figure 103 . four carrier at 70 mhz output ?120 st art 0hz res bw 20khz vbw 20khz sweep 27.9s (1001 pts) ref ?20dbm stop 1.1ghz ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?30 ?40 ?20 y ?15.917dbm () C66.430db () C67.401db x 91mhz () 49mhz () 1 17.9mhz function v alue ?15.919dbm () C66.658db () C67.436db function width 6mhz 6mhz 6mhz function band power band power band power mode n 1 1 trc 1 1 1 sc l f f () f () 1 21 31 11 149- 1 15 10db/div figure 104 . eight carrier at 70 mhz output 11 149-2 11 ?12 0 ?3 0 st ar t 0hz res bw 20k hz vbw 2k hz sweep 27 . 9s ( 1001 p ts) ref ?20 dbm stop 1.1ghz ?1 10 ?10 0 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ? 20 ?4 0 y ? 6.221 dbm ( ) ?68.115 db ( ) ?71 . 783 db x 95 0mhz ( ) ? 68 mhz ( ) ?882 mhz f unc t io n value ? 6.223 dbm ( ) ? 68.115 db ( ) ?71 . 783 db f unc t io n width 6mhz 6mhz 6mhz f unc t io n band power band power band power mode n 1 1 trc 1 1 1 scl f f f 2 1 1 3 1 10db/div figure 105 . single carrier at 950 mhz outp ut ?120 ?30 st art 0hz res bw 20khz vbw 2khz sweep 27.9s (1001 pts) ref ?20dbm stop 1.1ghz ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?20 ?40 y ?14.583dbm () C65.064db () C71.759db x 959mhz () C77mhz () C891mhz function v alue ?14.584dbm () C65.064db () C71.759db function width 6mhz 6mhz 6mhz function band power band power band power mode n 1 1 trc 1 1 1 sc l f f f 21 1 31 11 149- 1 17 10db/div figure 106 . four carrier at 950 mhz output ?120 st art 0hz res bw 20khz vbw 2khz sweep 27.9s (1001 pts) ref ?20dbm stop 1.1ghz ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?30 ?40 ?20 y ?18.364dbm () C63.858db () C70.065db x 971mhz () C89mhz () C903.0mhz function v alue ?18.364dbm () C63.858db () C70.065db function width 6mhz 6mhz 6mhz function band power band power band power mode n 1 1 trc 1 1 1 sc l f f f 21 1 31 11 149- 1 18 10db/div figure 107 . eight carrier at 950 mhz output
ad9119/ad9129 data sheet rev. 0 | page 32 of 68 i outfs = 33 ma, f dac = 2.782 gsps, nominal supplies, t a = 25c, unless otherwise noted. 0 0.2 0.4 f out (ghz) in-band second harmonic (dbc) 0.6 1.0 0.8 ?40 ?50 ?60 ?70 ?80 ?90 11 149- 1 19 figure 108 . second harmonic vs. f out performance for one docsis c arrier 0 0.2 0.4 f out (ghz) in-band second harmonic (dbc) 0.6 1.0 0.8 ?40 ?50 ?60 ?70 ?80 ?90 11 149-120 figure 109 . second harmonic vs. f out performance for four docsis carriers 0 0.2 0.4 f out (ghz) in-band second harmonic (dbc) 0.6 1.0 0.8 ?40 ?50 ?60 ?70 ?80 ?90 11 149-121 figure 110 . second harmonic vs. f out pe rformance for eight docsis carriers 0 0.2 0.4 f out (ghz) in-band third harmonic (dbc) 0.6 1.0 0.8 ?40 ?50 ?60 ?70 ?80 ?90 11 149-122 figure 111 . third harmonic vs. f out performance for one docsis carrier 0 0.2 0.4 f out (ghz) in-band third harmonic (dbc) 0.6 1.0 0.8 ?40 ?50 ?60 ?70 ?80 ?90 11 149-123 figure 112 . thi rd harmonic vs. f out performance for four docsis carriers 0 0.2 0.4 f out (ghz) in-band third harmonic (dbc) 0.6 1.0 0.8 ?40 ?50 ?60 ?70 ?80 ?90 11 149-124 figure 113 . thi rd harmonic vs. f out performance for eight docsis carriers
data sheet ad9119/ad9129 rev. 0 | page 33 of 68 i outfs = 33 ma, f dac = 2.782 gsps, nominal supplies, t a = 25c, unless otherwise noted. 0 0.2 0.4 f out (ghz) acpr (dbc) 0.6 1.0 0.8 ?50 ?55 ?65 ?75 ?85 ?60 ?70 ?80 ?90 11 149-219 acp1 acp2 acp3 acp4 acp5 figure 114 . single - carrier acpr vs. f out 0 0.2 0.4 f out (ghz) acpr (dbc) 0.6 1.0 0.8 ?50 ?55 ?65 ?75 ?85 ?60 ?70 ?80 ?90 11 149-220 acp1 acp2 acp3 acp4 acp5 figu re 115 . four - carrier acpr vs. f out 0 0.2 0.4 f out (ghz) acpr (dbc) 0.6 1.0 0.8 ?50 ?55 ?65 ?75 ?85 ?60 ?70 ?80 ?90 11 149-221 acp1 acp2 acp3 acp4 acp5 figure 116 . eight - carrier acpr vs. fout 0 0.2 0.4 f out (ghz) acpr (dbc) 0.6 1.0 0.8 ?50 ?55 ?65 ?75 ?85 ?60 ?70 ?80 ?90 11 149-222 acp1 acp2 acp3 acp4 acp5 figure 117 . 16 - carrier acpr vs. f out 1 2 3 5 7 4 f out (ghz) acpr (dbc) 6 98 ?50 ?55 ?65 ?75 ?85 ?60 ?70 ?80 ?90 11 149-223 acp1 acp2 acp3 acp4 acp5 figure 118 . 32 - carrier acpr vs. f out
ad9119/ad9129 data sheet rev. 0 | page 34 of 68 i outfs = 33 ma, f dac = 2.782 gsps, nominal supplies, t a = 25c, unless otherwise noted. ?120 center 77mhz res bw 10khz vbw 1khz sweep 6.08s (1001 pts) ref ?20dbm sp an 60mhz ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?30 ?40 ?20 11 149-125 10db/div figure 119 . gap channel aclr at 77 mhz 0 0.2 0.4 f out (ghz) aclr in ga p channe l (dbc) 0.6 1.0 0.8 ?40 ?50 ?60 ?70 ?80 ?90 11 149-225 figure 120 . gap channel aclr vs. f out
data sheet ad9119/ad9129 rev. 0 | page 35 of 68 terminology linea rity error (integral nonlinearity or inl) the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. differential nonlinearity (dnl) the measure of the variation in analog value, no rmalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a dac is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output cu rrent from the ideal of zero . for ioutp, 0 ma output is expected when the inputs are all 0s. for ioutn, 0 ma output is expected when all inputs are set to 1. gain error the difference between the actual and ideal output span. the actual span is determined by the output when a ll inputs are set to 1 minus the output when all inputs are set to 0. output compliance range the range of allowable voltage at the output of a current output dac. operation beyond the maximum compliance limits may cause either output stage saturation or b reakdown, resulting in nonlinear performance. temperature drift specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full - scale range (fsr) per degree celsius ( c ) . for reference drift, the drift is reported in ppm per c. power supply rejection the maximum change in the full - scale output as the supplies are varied from nominal to minimum and maximum specified voltages. spurious - free dynamic range the d ifference, in decibels (db), between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. total harmonic distortion (thd) the ratio of the rms sum of the first six harmonic components to the rms value of the mea sured input signal. it is expressed as a percentage or in decibels (db). noise spectral density (nsd) t he converter noise power per unit of bandwidth. this is usually specified in dbm/hz in the presence of a 0 dbm full - scale signal. adjacent channel leaka ge ratio (aclr) the ratio, in dbc, between the measured power within a channel rel ative to its adjacent channels. adjacent channel power ratio (acpr) the ratio , in dbc, between the total power of an adjacent channel ( inter modulation signal ) to the main channel's power (useful signal). modulation error ratio (mer) a measure of the discrepancy between the average output symbol magnitude and the rms error magnitude of the individual symbol. modulated signals create a discrete set of output values referred to as a constellation, and each symbol creates an output signa l corresponding to one point on the constellation. intermodulation distortion (imd) t he result of two or more signals at different frequencies mixing together. many products are created according to the formula af1 bf2, where a and b are integer values.
ad9119/ad9129 data sheet rev. 0 | page 36 of 68 serial communication s port overview the ad9119 / ad9129 are 11- bit/14 - bit dac s that operate at an update rate of up to 2.8 gsps. due to internal timing requirements , the minimum allowable sample rate is 1400 msps. input data is sampled through two 11 - /14 - bit lvds ports that are internally multiplexed. each port has its own data inputs, but both ports share a common data clock input (dci) . the lvds inputs meet the iee e- 1596 specification with the exception of input hysteresis, which is not guaranteed over all process corners. each dci input runs at one - quarter the input data rate in a double data rate (ddr) format. each edge of the dci is used to transfer data into the ad9119 / ad9129 . the dacclk_n and dacclk_p inputs directly drive the dac core to minimize clock jitter. the dacclk signal is divided by 4 and then output as the dco for each port. the dco signal can be used to clock the data source. the dac expects ddr lvds data ( p0_d [13:0] x, p1 _d [13:0] x ), with each channel aligned with the single ddr dci signal. control of the ad9119 / ad9129 functions is via a spi . serial p eripheral interface (spi) the ad9119 / ad9129 spi is a flexible, synchronous serial c ommunications port, allowing easy interface to many industry - standard microcontrollers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, including the motorola? spi and the intel? ssr protocols. the interface allows read/write access to all registers that configure the ad9119 / ad9129 . most significant bit first (msb - first) or least significant bit first (lsb - first) transfer form ats are supported. the ad9119 / ad9129 serial interface port can be configured as a single i/o pin (sdio) or two unidirectional pins for input/ output (sdio and sdo). sdo (pin j2) sdio (pin j1) sclk (pin k1) cs (pin k2) ad9119/ ad9129 spi port 11 149-126 figure 121 . ad9119 / ad9129 spi port general operation of the spi there are two phases to a communication cycle with the ad9119 / ad9129 . phase 1 is the instruction cycle, which is the writing of an instruction byte into the ad9119 / ad9129 , coincident with the first eight sclk rising edges. the instruction byte provides the ad9119 / ad9129 serial port controller with informat ion about the data transfer cycle, which is phase 2 of the communi - cation cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write and the starting register address for the first byte of the data transfer. the first e ight sclk rising edges of each communication cycle are used to write the instruction byte into the ad9119 / ad9129 . the remaining sclk edges are for phase 2 of the co mmunication cycle. phase 2 is the actual data transfer between the ad9119 / ad9129 and the system controller. phase 2 of the communication cycle is a transfer of one byte only. single - byte data transfers are useful to reduce cpu overhead when register access requires one byte only. registers change immediately upon writing to the last bit of each transfer byte. cs (chip select) can be raised after ea ch sequence of eight bits (except the last byte) to stall the bus. the serial transfer resumes when cs is lowered. stalling on nonbyte boundaries resets the spi. instruction mode (8 - bit instruction) the instruction byte is shown in the fo llowing table. msb lsb i7 i6 i5 i4 i3 i2 i1 i0 r/w a6 a5 a4 a3 a2 a1 a0 r/w, bit 7 of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. logic 1 indicates a read ope ration. logic 0 indicates a write operation, the data transfer cycle. a6 to a0 ( bit 6 through bit 0 of the instruction byte ) determine which register is accessed during the data transfer portion of the communications cycle. serial peripheral interface pin descriptions sclk serial clock the serial clock pin is used to synchronize data to and from the ad9119 / ad9129 and to run the internal state machines. the maximum f requency of sclk is 20 mhz. all data input to the ad9119 / ad9129 is registered on the rising edge of sclk. all data is driven out of the ad9119 / ad9129 on the rising edge of sclk. cs chip select active low input starts and gates a communication cycle. it allows more than one device to be used on the same seria l communi - cations lines. the sdo and sdio pins go to a high impedance state when this input is high. chip select should stay low during the entire communication cycle. sdio serial data i/o data is always written into the ad9119 / ad9129 on this pin. however, this pin can be used as a bidirectional data line. the configuration of this pin is controlled by r egister 0x00 , bit 7 (sdio_dir). the default is logic 1, which co nfigures the sdio pin as bi directional. sdo serial data out data is read from this pin for protocols that use separate lines for transmitting and receiving data. when the ad9119 / ad9129 are operating in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state.
data sheet ad9119/ad9129 rev. 0 | page 37 of 68 msb/lsb transfers the ad9119 / ad9129 serial port can support both msb - first and lsb - first data formats. this functionality is controlled by the lsb/msb bit , bit 6 in register 0x00 . the default is msb first (lsb/msb = 0). when the msb - first data format is selected , the instruction a nd data bytes must be written from the most significant bit to the least significant bit. when lsb/msb = 1 (lsb first), the instruction and data bytes must be written from the least significant bit to the most significant bit. serial port configur ation t he ad9119 / ad9129 serial port configuration is controlled by register 0x00 , bits[7:5]. note that the configuration changes immediately upon writing to the last bit o f the register. when setting the software reset bit (s oftreset in register 0x00 , bit 5), all registers are set to their default values except register 0x00 , which remains unchanged. in the event of unexpected programming sequences, the ad9119 / ad9129 spi can become inac cessible. for example, if user code inadvertently changes the lsb/msb bit, the bits that follow experience unexpected results. the spi can be returned to a known state by writing an incomplete byte (1 to 7 bits) of all 0s , followed by three bytes of 0x00 . this returns to the msb - first instructions (register 0 x00 = 0x00) so that the device can be reinitialized. r/w a6 a5 a4 a3 a2 a1 a0 d7 n d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle data transfer cycle sclk sdio cs 11 149-127 figure 122 . serial register interface timing, msb - first write r/w a6 a5 a4 a3 a2 a1 a0 d7 inst ruc t io n cycle data t ran sfer cycle sclk sdio sdo d7 cs 11 149-128 d6 n d5 n d0 0 d1 0 d2 0 d3 0 d6 n d5 n d0 0 d1 0 d2 0 d3 0 figure 123 . serial register interface timing, msb - first read a0 a1 a2 a3 a4 a5 a6 r/w sclk sdio cs inst ruc t io n cycle data t ran sfer cycle 11 149-129 d7 n d6 n d5 n d0 0 d1 0 d2 0 d4 0 figure 124 . serial register interface timing, lsb - first write a0 a1 a2 a3 a4 a5 a6 r/w d0 inst ruc t io n cycle data t ran sfer cycle sclk sdio sdo d0 cs 11 149-130 d7 n d6 n d5 n d1 0 d2 0 d4 0 d7 n d6 n d5 n d1 0 d2 0 d4 0 figure 125 . serial register interface timing, lsb - first read inst ruc t io n bit 6 inst ruc t io n bit 7 sclk sdio t ds t ds t dh t sclk cs 11 149-131 figure 126 . timing diagram for an spi register write i1 i0 d7 d6 d5 t dv t dn v sclk sdio cs 11 149-132 figure 127 . timing diagram for an spi register read after the last instruction bit is written to the sdio pin, the driving signal must be set to a high impedance in time for the bus to turn around. the serial output data from the ad9119 / ad9129 is enab led by the falling edge of sclk. this causes the first output data bit to be shorter than the remaining data bits, as shown in figure 127 . to assure proper reading of data, read the sdio pin or the sdo pin before changing sclk f rom low to high. due to the more complex multibyte protocol, multiple ad9119 / ad9129 devices cannot be daisy - chained on the spi bus. control m ultiple dacs by using independent cs signals.
ad9119/ad9129 data sheet rev. 0 | page 38 of 68 t heory of operation the ad9119 / ad9129 are 11- bit/14 - bit dac s that are capable of reconstructing signal bandwidths up to 1 .4 ghz while operating with an input data rate up to 2.8 gsps. figure 128 shows a top level functional diagram of the ad9119 / ad9129 . a h igh perfor - mance nmos dac delivers a signal dependent, differential current to a balanced external load referenced a nominal 1.8 v analog supply. the current source array of the dac is referenced to an external ?1.5 v supply, and its full - scale current, i o utfs , can be adjusted over a 9.5 ma to 34.4 ma span. 11 149-133 sdo sdio sclk cs dci_x data assembler spi reset tx dac core data latch ioutp ioutn irq 4 fifo 2 baseband mode mix- mode frm_x (frame/ parity) ad9129 clock distribution vref i250u lvds ddr receiver lvds ddr receiver p1_d[13:0]p, p1_d[13:0]n p0_d[13:0]p, p0_d[13:0]n dl l 1.2v pll dco_x normal dacclk_x dcr figure 128 . functional block diagram of the ad9119 / ad9129 a low jitter differential clock receiver is used to square up the signal appearing at the dacclk _x input that sets the update rate of the dac. the differential clock receiver can accept sinusoidal signals with negligible noise spectral density degra - dation if the input signal level is maintained above 0 dbm. a +1 db degradation occurs at a ? 5 dbm input, and degradation increases as the signal approaches ? 10 dbm and its associated + 2 db additional degra dation . a duty cycle restorer (dcr), following the clock receiver, ensures near 50 % duty - cycle to the subsequent circuitry. the output of the dcr serves as the master clock and is routed directly to the dac, as well as to a clock distribution block that generates all critical internal and external clocks. the clock source quality, as de fined by its phase noise characteristics, jitter, and drive capability, is an important consideration in maintaining optimum ac performance. the ad9119 / ad9129 supp orts a source synchronous, lvds double data - rate (ddr) data interface to the host processor. two 11 - bit/14 - bit lvds data ports (p0_d xp, p0_dxn and p1_d x p, p 1 _ d x n ) are used to sample de - interleaved data from the host on the rising and falling edge of the ho st dci clock. this effectively reduces the bus interface speed to ? the data rate (for example, f data /2) with the dci clock operating at f data /4. an optional parity bit can also be sent along with the data to enhance the robustness of the interf ace. in this case, a counter is available to count parity errors and generate an interrupt request (irq) when a programmable threshold is exceeded. the ad9119 / ad9129 provi de the host with a dco clock that is equal to the dci clock frequency to establish synchronous opera - tion. a delay locked loop (dll) with programmable phase offset is used to generate an internal sampling clock with optimum edge placement for the input dat a latches of the lvds ddr receivers. when data is latched into the ad9119 / ad9129 , an eight - sample - deep fifo is used to hand off the data between the host and the ad9119 / ad9129 clock domains. the fifo can be reset with an external synchronization signal, f sync , to ensure consistent pipeline latency. the pipeline delay , from a s ample being latched into the data port to when it appears at the dac output , varies depending on the chosen configuration (see the pipeline delay (latency) section). the de - interleaved data is reassembled into its original data stream after passing into the internal clock domain of the ad9119 / ad9129 . because the quad - switch architecture of the dac updates its output on both the rising and falling edge (for example, dual edge clocking) of the dacclk signal , the following two additional mo des of operation are available: ? a 2 interpolation filter can be selected to increase the effective dac update rate (f dac ) to be 2 the input data rate, he nce simplifying the analog post filtering require - ments and reducing the effects of alias harmonics in the desired baseba nd region. ? a mix -m ode option essentially generates the complement sample on the falling edge such that the original nyquist spectrum is shifted to f dacclk , with the s inc null of the dac falling at 2 f dacclk . the digital handoff betwe en the digital domain and mixed signal domain of a high speed dac is critical in preserving its output dynamic range. a phase locked loop (pll) with programm able phase offset is used to optimize the timing handoff between these two clock domains. state machines are used to initialize both the dll and the pll during the initial boot sequence after receiving a stable dacclk signal. following initialization of th e two loops , they maintain optimum timing alignment over temperature, time, and power supply variation. the ad9119 / ad9129 also provide irq capability to monitor the dll, the pll, and other internal circuitry.
data sheet ad9119/ad9129 rev. 0 | page 39 of 68 lvds data port inter face the ad9119 / ad9129 can operate with input data rates of up to 2.8 gsps. a source synchronous lvds interface is used between the host and the ad9119 / ad9129 to achieve these high data rates , while simplifying the interface. as shown in figure 129, the host feeds the ad9119 / ad9129 with de - interleaved input data into two 11 - bit/14 - bit lvds data ports (p0_dxp, p0_dxn and p1_dxp, p1_dxn) at ? the dac clock rate (that is, f dacclk /2). along with the input data, the host provides an embedded ddr data clock input (dci _x ) at f dacclk /4. a dll circuit that is designed to operate with dci clock rates of between 350 mhz and 700 mhz is used to generate a ph ase shifted version of dci, called the data sampling clock (dsc), to register the input data on both the rising and falling edges. as shown in figure 130 , the dci clock edges must be coincident with the data bi t transitions wit h minimum skew and jitter. the nominal sampling point of the input data occurs in the middle of the dci clock edges because this point corresponds to the center of the data eye. this is also equivalent to a nominal phase shift of 90 of the dci clock. the data timing requirements are defined by a minimum data valid margin that is dependent on the data clock input skew, input data jitter, and the variations of the dll delay line across delay settings. this margin is defined by subtracting from the data perio d any data skew , da ta jitter, and the keep - out window (kow) that is defined by th e sum of the set and hold times, as follows: t data valid margin = t data period ? t data skew ? t data jitter ? (t h + t s ) the keep - out window , which is t he sum of the set and hol d times, is the area where data transitions should not occur . the timing margin allows tuning of the dll delay setting , either automatically or in manual mode (see figure 130). figure 130 shows that t he ideal location for the dsc signal is 90 out of phase from the dci input. however, due to skew of the dci relative to the data, it may be necessary to change the dsc phase offset to sample the data at the center of its eye diagram. the sampling instance can be varied in discrete increments by offsetting the nominal dll phase shift value of 90 via register 0x0a , bits[3:0]. the following equation define s the phase offset relationship: phase offset = 90 n 11.25 , | n | < 8 l vds ddr receiver dci dco clock distribution delay lock loop l vds ddr receiver p1_d[13:0]x p0_d[13:0]x ad9129 host processor lvds ddr driver 14 2 14 2 1 2 1 2 data de-interleaver f data = f dacclk /2 f dco = f dacc lk /4 f dci = f dacc lk /4 f dacclk even data samples odd data samples optional parity combined odd/even parity bit 11 149-134 figure 129 . recommended digital interface between the ad9119 / ad9129 and the host processor input data[13:0] dci dll phase delay t data period t data skew t dsc setup and hold t data jitter data sample clock data eye 11 149-135 figure 130 . lvds data port timing requirements
ad9119/ad9129 data sheet rev. 0 | page 40 of 68 figure 131 shows the dsc set and hold times with respect to the dci signal and data signals. 11149-238 dci data dsc t s t h figure 131 . lvds data port set and hold times table 11 shows the typical t imes for variou s dac clock frequencies that a re required to calculate the data valid margin . the amount of margin that is available for tuning of the dsc sampling point can be determined using table 11 . table 10 lists the values that are guaranteed over the operating conditions. these values were taken with 50% duty cycle and dci swing of 450 mv p- p. for best performance, the duty cycle variation should be kept below 5%, and the dci input should be a s high as possible, up to 800 mv p-p. table 10 . data port set and hold time window (guaranteed) frequency, f dac (mh) time (ps) data port set and hold times (ps) at dll phase 3 0 3 1600 t s ? 272 ? 489 ? 683 t h 682 911 1120 2300 t s ? 168 ? 292 ? 420 t h 564 705 839 2800 t s ? 88 ? 185 ? 285 t h 457 559 652 table 11 . data port set and hold time window ( typical ) frequency , f dac 1 (mh) time (ps) data port set and hold times (ps) at dll phase 6 5 4 3 2 1 0 1 2 3 4 5 6 1400 t s ? 106 ? 205 ? 274 ? 353 ? 436 ? 523 ? 604 ? 680 ? 798 ? 906 ? 993 ? 1064 ? 1131 t h 426 499 571 651 730 813 900 977 1069 1152 1235 1303 1387 1500 t s ? 124 ? 197 ? 291 ? 351 ? 453 ? 524 ? 600 ? 670 ? 732 ? 815 ? 908 ? 982 ? 1071 t h 427 490 556 637 713 795 870 942 1025 1100 1181 1241 1320 1600 t s ? 120 ? 191 ? 252 ? 335 ? 402 ? 495 ? 552 ? 626 ? 704 ? 776 ? 847 ? 902 ? 978 t h 421 485 550 619 689 760 836 910 989 1049 1128 1195 1250 1700 t s ? 111 ? 184 ? 226 ? 301 ? 370 ? 442 ? 528 ? 580 ? 641 ? 719 ? 784 ? 822 ? 895 t h 382 429 489 549 619 700 762 825 907 970 1032 1095 1151 1800 t s ? 93 ? 133 ? 209 ? 265 ? 326 ? 401 ? 475 ? 524 ? 596 ? 646 ? 709 ? 765 ? 823 t h 400 442 492 555 617 677 754 816 883 950 1003 1061 1122 1900 t s ? 90 ? 139 ? 182 ? 254 ? 298 ? 359 ? 430 ? 496 ? 547 ? 593 ? 663 ? 700 ? 765 t h 398 443 488 535 593 664 717 778 849 900 963 1021 1070 2000 t s ? 82 ? 122 ? 170 ? 220 ? 272 ? 346 ? 399 ? 452 ? 517 ? 565 ? 607 ? 660 ? 713 t h 389 423 468 522 571 625 683 733 789 854 908 958 1015 2100 t s ? 87 ? 133 ? 161 ? 206 ? 274 ? 331 ? 384 ? 443 ? 488 ? 540 ? 586 ? 623 ? 675 t h 370 409 451 491 536 592 636 696 751 794 855 911 954 2 200 t s ? 94 ? 143 ? 182 ? 245 ? 283 ? 334 ? 378 ? 427 ? 487 ? 521 ? 565 ? 604 ? 659 t h 415 453 487 523 571 622 673 722 778 818 859 9 08 956 2 300 t s ? 93 ? 131 ? 182 ? 227 ? 270 ? 312 ? 357 ? 388 ? 439 ? 485 ? 531 ? 570 ? 623 t h 390 422 456 500 542 595 644 686 731 778 821 858 902 2400 t s ? 130 ? 156 ? 196 ? 244 ? 277 ? 313 ? 366 ? 404 ? 457 ? 496 ? 534 ? 560 ? 615 t h 426 459 494 529 567 607 653 698 731 76 9 815 862 911 2500 t s ? 73 ? 106 ? 142 ? 177 ? 216 ? 258 ? 308 ? 348 ? 394 ? 430 ? 458 ? 486 ? 535 t h 370 407 433 467 502 546 582 619 662 702 740 780 828 2600 t s ? 43 ? 76 ? 115 ? 145 ? 184 ? 228 ? 275 ? 306 ? 351 ? 375 ? 402 ? 443 ? 491 t h 338 369 396 430 466 503 535 567 6 14 652 690 725 766 2700 t s ? 54 ? 77 ? 108 ? 144 ? 179 ? 228 ? 277 ? 305 ? 336 ? 354 ? 400 ? 424 ? 471 t h 316 340 372 406 441 475 499 539 580 622 654 685 729 2800 t s ? 36 ? 72 ? 101 ? 143 ? 175 ? 208 ? 243 ? 287 ? 320 ? 347 ? 382 ? 408 ? 463 t h 335 355 379 404 442 480 511 5 45 575 607 638 676 717 1 table 11 shows characterization data for selected f dac frequencies. other frequencies are possible, and table 11 can be used to estimate performance.
data sheet ad9119/ad9129 rev. 0 | page 41 of 68 maximizing the opening of the eye in both the dci and data signals improves reliability of the data port interface. use d iffer - ential controlled impedance traces of equal length (that is, delay) between the host processor and th e ad9119 / ad9129 input. to ensure coincident transitions with the data bits, implement the dci as an additional data line with an alternating (010101) bit sequence from the same outpu t drivers that are used for the data. for synchronous operation between the host and the ad9119 / ad9129 , the ad9119 / ad9129 provide a data clock output, dco, to the host at the same rate as dci (that is, f dacclk /4). note that the dci signal can have arbitrary phase alignment with respect to the dco because th e dll of the ad9119 / ad9129 ensures proper data hand - off between the two clock domains (that is, the host processors and the internal digital core of the ad9119 / ad9129 ). the default reset state of the ad9119 / ad9129 is to have the dco si gnal disabled. to enable it, write a 1b to register 0x0c, bit 6. the dco output level is controlled in register 0x7c , bits[7:6]. the default setting is 01b, or 2.8 ma, but it can be increased to as high as 4 ma (11b) if higher swing is necessary. the dci s ignal is ac - coupled internally; therefore, a possibility exists that removing the dci signal can cause dac output chatter due to randomness on the dci input. to avoid this chatter, it is recommended that the dac output be disabled when the dci signal is no t present. to do this, program the dac output current power - down bit in register 0x01 , bit 6, to 1b. when the dci signal is again present, the dac output can be enabled by programming register 0x01 , bit 6, to 0b. the dac output powers up in ~2 s. the stat us of the dll can be polled by reading the data status register at address 0x0e . bit 0 indicates that the dll is running and attempting lock, and bit 7 is set to 1b when the dll is locked. bit 2 is set to 1b when a valid data clock is detected. the warning bits in address 0x0e, bits[6:4 ] can be used as indicators that the dac may be operating in a nonideal location in the delay line. note that these bits are read at the spi port speed, which is much slower than the actual speed of the dll. this means that t hese bits can show only a snapshot of what is happening, rather than giving real - time feedback. temperature effects the length of the delay line varies slightly across the operating temperature range, as the amount of delay through a delay cell expands or contracts slightly due to the temperature change. this can introduce a situation where the dll may lock at one temperature extreme and then approach an unlocked state as the temperature changes (see figure 132 ). in the example shown in figure 132 , the dll can lock at phase s etting 0 at 90 in a cold temperature. as the temperature gets hotter, the delay line changes length , and the controller adjusts the dll control voltage to keep the 90 offset. in this case, a voltage beyond the acceptable control voltage range is required to hold the 90 phase offset. before losing lock, the dll controller issues a dll warning by setting register 0x0e , bit 6, to 1b and setting either bit 5 or bit 4 to 1b . this set ting indicates that the dll is near to losing lock. if the dll is going to reach the begi nning of the delay line soon , the controller issues a start warning by setting register 0x0e , bit 5 and bit 6 to 1b. this setting indicates that the dll is at the star t of the delay line, and losing lock is imminent. d0 d1 user dci user data data sample clk 90 delay line ? cold delay line ? hot 1 1149-236 figure 132 . example of dll length variation across temperature a similar situation can happen at the end of the delay line, in which case a dll warning and a dll end is issued. dl l end is indicated when register 0x0e , bit 4 and bit 6 are set to 1b. in case of a dll warning, action must be taken to prevent loss of lock. on a start warning, reduce the minimum delay of the delay line by removing one or several of the delay cells. this can be accomplished by setting the bits in registers 0x70 and register 0x71 to 0b. begin by setting bit 0 of register 0x70 to 0b, then bit 1, and so on. in some cases, up to three delay cells may need to be disabled. it is possible to disable up to six delay cells. however, in most cases, none of the cells need to be disabled. the situation varies, depending on the temperature r ange needed , as well as the dac clk signal rate used. the end warning case is a theoretical possibility, but practical conditions n ormally dictate that it is not reachable. if the e nd warning is reached, the dll must be relocked immediately. when doing initial lock (or relock) of the dll, all delay cells must be active, with all delay cell bits in register 0x70 and register 0x71 set t o 1b. parity the data interface can be continuously monitored by enabling the parity bit feature in register 0x5c , bit 7 , and configuring the frm_p, frm_n pins ( pin k13 and pin k14 ) as p arity pins by setting register 0x07 , bits[1:0] = 1 dec. when this pin con - figuration is used , the host send s a parity bit along with each data sample. this bit is set according to the following formulas , where n is the data sample that is being checked. for even parity on the ad91 29 , xor[frm( n), p0_d0(n), p0_d1(n), p0_d2(n), ..., p0_d13(n), p1_d0(n), p1_d1(n), p1_d2(n), , p1_d13(n) ] = 0. for odd parity on the ad9129 , xor[frm(n), p0_d0(n), p0_d1(n), p0_d2(n), ..., p0_d13(n), p1_d0(n), p1_d1(n), p1_d2(n), , p1_d13(n) ] = 1.
ad9119/ad9129 data sheet rev. 0 | page 42 of 68 for the ad9119 , the data port is 11 - bit instead of 14 - bit, so p0_d11, p0_d12, p0_d13, p1_d11, p1_d12, and p1_d13 are not used in the calculation of the parity bit. thus , the parity bit is calculated over 29 bits (including the frame/parity bit) for the ad9129 and over 23 bits for the ad9119 . if a parity error occurs, the parity error counter ( register 0x5d or register 0x5e) is incremented. parity errors on the bits that are sampled by the rising edge of dci increment the parity rising e dge error counter (reg ister 0x5d ) and set the parity e rr or rising edge bit ( register 0x5c , bit 0 ). parity errors on the bits that are sampled by the falling edge of dci increment the parity falling edge error counter (register 0x5e) and set the parity error falling edge bit (reg ister 0x5c , bit 1 ). the parity counter continues to accumulate until it i s cleared , or until it reaches a maximum value of 255. the co unt can be cleared by writing 1b to register 0x5c , bit 5 . an irq can be enabled to trigger when a parity error occurs by writing 1b to register 0x04 , bit 2 for rising edge - based parity detection or to register 0x04 , bit 3 for falling edge - based parity. the status of irq can be measured via register 0x06 , bit 2 or register 0x06 , bit 3 or by using the irq pin . when using the irq pin and more than on e irq is enabled, check register 0x06 , bits [3:2] wh en an irq event occurs to determine whether the irq was caused by a parity error. the irq c an also be cleared by writing 1b to register 0x06 , bit 2 or register 0x06 , bit 3 . the parity bit feature can also be used to validate the interface timing. as descri bed previously, the host provide s a parity bit with the data samples and configure s the ad9119 / ad9129 to generate an irq. the user can then sweep the sampling insta nce of the ad9119 / ad9129 input registers to determine at what point a sampling error occur s. d igital datap ath d escription figure 133 pro vides a more detailed diagram of the ad9119 / ad9129 digital data path. the 22 - bit/ 28- bit data path with internal ddr clock ing interfaces with the dual 11 - bit /14 - bit i nput data ports. because two 11 - bit /14 - bit samples are captured on each clock edge of dci, four consecutive samples are captured per dci clock cycle. samples captured on the rising edge of dci propagate through the upper section at a rate of dacclk/2 (ddr) , and those captured on the falling edge propagate through the lower section. 14 14 14 14 14 14 28 parity/ sed logic input latch input latch reg 0 reg 1 reg 2 reg 3 reg 4 reg 5 reg 6 reg 7 reset l ogi c f ra me spi fifo a lign re qu est re g 0x1 1[7] spi fifo a lign acknowledge re g 0x1 1[6] fifo write pointer o ff set re g 0x1 2[ 2:0] rd ptr reset wr ptr reset rd ptr reset dacclk/4 wr ptr reset dacclk/4 dist. dacclk/4 dll dci data frame/ parity frame 14 14 14 bits 28 1 28 1 reg 0 reg 1 reg 2 reg 3 reg 4 reg 5 reg 6 reg 7 fifo ph3 parity/ sed logic data assembler to dac decode mix-mode fifo ph1 fifo ph2 fifo ph0 11 149-136 2 figure 133 . digital datap ath of the ad9119 / ad9129
data sheet ad9119/ad9129 rev. 0 | page 43 of 68 after the input data has been captured, the data is passed through a logic block that monitors and/or determines the signal integrity of the high speed digital data interface. the optional parity check is used to continuously monitor the digital interface on a sample - per - sample basis, and the sample error detection (sed) can be used to validate the input data interface for system debug/ test purposes. note that the frame and parity signals share the same pin assignment because the frame signal is typically used during system initialization (for fifo synchronization purposes), and parity is used in normal operation. fifo description the ne xt functional block in the data path is a set of four fifos that are eight registers deep. the dual port data is clocked into th e fifos on both the rising and the falling edge of the dci signal. the fifo acts as a buffer that absorbs timing variations between the data source and dac, such as the clock - to - data variation of an fpga or asic. for the greatest timing margin, maintain th e fifo level near half full (that is, a difference of four between the write and read pointers). the value of the write pointer determines the fifo register into which the input data is written, and the value of the read pointer determines the register fro m which data is read and fed into the data assembler. the write and read pointers are updated every time new data is loaded and removed, respectively, from the fifo. valid data is transmitted through the fifo as long as the fifo does not overflow or become empty. note that an overflow or empty condition of the fifo is the same as the write pointer and read pointer being equal. when both pointers are equal, an attempt is made to simultaneously read and write a single fifo register . this simultaneous register access leads to unreliable data transfer through the fifo and must be avoided by ensuring that data is written to the fifo at the same rate that data is read from the fifo, keeping the data level in the fifo constant. this condition must be met by ensuri ng that dci is equal to dacclk/4 (or equivalently, dco). resetting the fifo data level fifo initializati on is required to ensure a four - sample spacing and a deterministic pipeline latenc y. if the clocks are running at power - up, the fifo initialize s to 50% full. the ad9119 / ad9129 has an internal delay that effectively offsets the fifo pointers by 2, such that the optimal fifo data level of 4 (center) reads back as 2 (0000011b) from register 0x13 to register 0x16 . to achieve this level , set register 0x12 to 0x2 0 (hexadecimal) before resetting the fifo . this sets the read pointer to l evel 2 and the write pointer to level 0. to maximize the timing margin between the dci input and the internal dac data rate clock, initialize the fifo data level before beginning data transmission. the value of the fifo data level can be initialized in three ways: by resetting the device, by strobing the frm_x input, and via a write sequence to the serial port. the two preferred methods are use of the frame signal and via a write sequence to the serial port. before initializing the fifo data level, the lvds dll and th e dac clock pll must be locked. the frm_x input can be used to initialize the fifo data level value. first, set up the f rm_n and frm_p pins for frame mode ( reg ister 0x07 , bits [1:0] = 2). next , assert the frame signal high for at least one dci clock cycle. when the frame signal is asserted in this manner, the write poi nter is set to 4 (by default or to the fifo start level (register 0x12 , bits [2:0])) the next time the read pointer becomes 0 (see figure 134). 0 1 2 3 4 5 6 7 0 1 2 3 3 4 5 6 7 0 1 2 4 5 6 7 fifo write resets read pointer frame write pointer 11149-137 figure 134 . timing of the f rame input vs. write pointer value to initialize the fifo data level through the serial port, toggle bit 7 of register 0x11 from 0 b to 1 b . when the write to the register is complete, the fifo data level is initialized. the recommended procedure for a serial port fifo data level initialization is as follows: 1. request fifo level reset by setting register 0x11 , bit 7 , to 1b. 2. ve rif y that the part acknowledges the request by ensuring that register 0x11, bit 6 , is set to 1b. 3. remove the request by setting register 0x11, bit 7 , to 0 b. 4. ve rif y that the part drops the acknowledge signal by ensuring that register 0x11, bit 6 , is set to 0b. monitoring the fifo status the relative fifo data levels can be read from register 0x13 through register 0x16 at any time. the fifo data level reported by the serial port is denoted as a 7 - bit thermometer code of the write counter state , relative to the absolute read counter being at 0. for example, the fifo data level of 2 is reported as a value of 0000011 b in the status register. adding the internal delay of 2 to this value makes the reported fifo level equal to 4. it should be noted that, depending on the timing relationship between dci and the main dacclk signal , the fifo level value can be off by a count of 1 . therefore, it is important that the difference between the rea d and write pointers be maintained at 2. multiple dac synchronization synchronization of multiple ad9119 / ad9129 s implies that all of the dac outputs are time alig ned to the same phase when all devices are fed with the same data pattern (along with dci) at the same instance of time. fifo initialization ensures that the initial pipeline latency in the fifo is set to four samples and remains at this level , assuming th at no process, voltage, or tem - perature variations occur between the host and the ad9119 / ad9129 clock domains.
ad9119/ad9129 data sheet rev. 0 | page 44 of 68 figure 136 shows an exa mple of two ad9119 / ad9129 devices that are synchronized to the same host ( that is, fpga and asic). note that, when the same resources are used to generate these out - put signals, synchronization to a single host ic ensures minimum data and dci time skew between devices . even after fifo initialization, a phase ambiguity exists between the read pointers of each device because the read counter of each device powers up in an arbitrary state. therefore, the exact instance when the respective write pointer is set to 4, after the frame signal is asserted, also remains ambiguous. it is possible for the read pointer of on e device to reach its 0 count several clock cycles before another device (see figure 134). synchronization within a data sample requires insight into the difference between the read pointers of the master and slave devices, as well as the ability to vary the delay of the slave device( s) within the host to compensate for initial offsets between devices. it is possible to calculate how many data samples the slave device(s) is offset from the master device for the following reasons: ? the pipeline delay of each device is the same after fifo initialization. ? the read counter of each device is derived from the same phase aligned dacclk source. ? the state of the read counters of each device is sampled at the same instance in time via the frame signal. ? the readback value (register 0x12 [6:4]) is normalized to a data sample (that is, a dacclk period). by calculating the difference between the read pointer settings of the master and slave devices, the user can advance or delay the data stream of the slave device within t he fpga. because this difference can be up to 4 data samples, the fpga must provide this adjustment range for dac synchronization alone. note that additional range must be added to compensate for any other system delay variation. in addition to synchroniz ing to the data sample level, the ad9119 / ad9129 can enable synchronization to the dacclk level (see figure 135 ). a 1.8 v cmos output pi n, sync, can be used to provide a dacclk/8 signal. using the sync output from each dac, enabled by register 0x1a, b it 4 = 1, the user can create a simple phase detector with an external xor gate. dac 1 sync dac 2 sync xor 11149-139 figure 135 . example of sy nchron ization of two dacs to 1 dacclk accuracy by adjusting the internal delay (incrementing or decrementing by one dacclk cycle with each write to register 0x1a, bit 7 or bit 6, respectively), the user can align the dacclks inside the two dacs to within 1 da cclk cycle , when errors from the external phase detector, low - pass filter, and delay differences are taken into account. the existing phase position can be read from register 0x1a, bits[2:0]. align t he sync outputs first, then reset the fifos on each dac t o ensure that proper sync is achieved. this calibra tion must be performed at each power - up because the fifos can be reset to any of four levels based on the div ide - by - 4 output of the clock distribution block (see figure 133) . fo r example, a fifo reset to l evel 2 could have an actual fifo level of 1.5, 1.75, 2, or 2.25 , based on the location of the div - by - 4 clock edge. adjusting the sync signals to align with each other eliminates this ambiguity. when the two dacs are aligned, the drift over temperature and supply voltage of the dacclk signal of one dac, relative to another dac, is expected to be no more than 450 ps. the dco signal is derived from th e sync signal such that if the sync signal is adjusted by a dacclk cycle, the dco signal must also be adjusted by the same amount. when all adjustments of the sync signal are complete, it is recommended to disable the sync output by programming register 0x1a , bit 4 = 0, to eliminate a possible source of clock spurious signals. ad9129 master dacclk matched delays dci adclk925 1.4ghz to 2.8ghz common clock source dco_x fpga dci_x frm_x ad9129 slave dacclk dco_x dci_x frm_x 0+ dbm 0+ dbm 11149-138 figure 136 . example of synchronization of two dacs to one fpga
data sheet ad9119/ad9129 rev. 0 | page 45 of 68 data assembler and signal processing modes the data assembler reconstructs the original sample sequence. it consists of a 4:1 multiplexer o perating at f dacclk . each of the four fifos provides a sample that is now referenced to the internal clock domain of the ad9119 / ad9129 , f dacclk . the reconstructed s ample sequence can be directed to the dac decode logic or undergo additional signal processing. in 2 interpolation mode, a fir filter is used to generate a new data sample that is inserted between each sample, such that it can update the dac decode logic on the falling edge of dacclk. in mix - mode, the complement of each data sample is generated and inserted after it, such that it also updates the dac in a similar manner. the 2 interpolator can be used with mix - mode enabled. 2 digital filter the ad9119 / ad9129 include a bypassable 2 half - band interpolation filter to help simplify the analog reconstruction filter. the filter has the potential benefit of minimizing th e impact of folded back harmonics in the desired baseband region. the filter operates in a dual - edge clocking mode , where it generates a new interpolated sample value for every alternate dacclk edge. this effectively increases the dac update rate to 2 f d acclk with the dacs sinc response null moving from f dacclk to 2 f dacclk . there are two different filters, fir25 and fir40, that can be chosen using register 0x18, bit 5 , when the 2 interpolator is enabled with register 0x18 , bit 7. the fir25 half - band filter provides 25 db of stop - band rejection. its response is shown in figure 137 . coefficients were optimized for practical implementation purposes with t he notion that the 0.5 db pass - band ripple effects on a multicarrier app lication (for example, docsis) can be compensated by the digital host adjusting individual chan nel powers. note that the worst - case tilt across any 6 mhz channel is less than ?0.05 db. the fir40 half - band filter provides 40 db of stop - band rejection, and its response is shown in figure 139 . coefficients were chosen to reduce pass - band ripple and increase out - of - band rejection for multicarrier applications (for example, docsis). as a result, the frequency response has a flatter i n- band response and a sharper transition region, and the trade - off is a higher phase count, leading to higher pipeline delay and higher power consumption. the two filters are compared in table 12 . table 12 . features of the two 2 interpolat ion filters filter ripple (db) atten uation (db) power (mw) fir25 0.5 25 150 fir40 0.1 40 450 a duty cycle restore circuit follows the dacclk clock receiver to minimize impact of duty cycle errors on image rejection. 0 500 1000 1500 2000 2500 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 frequenc y (mhz) magnitude (normalized to 0db) 11149-140 figure 137 . fir25 2 interpolation filter plot, complete frequency response; f dac = 2.5 ghz 0 200 400 600 800 1000 1200 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 frequenc y (mhz) magnitude (normalized to 0db) 11 149-141 figure 138 . fir25 2 interpolation filter plot, pass -b and ripple; f dac = 2.5 ghz 0 0.90.80.70.60.50.40.30.20.1 1.0 ?60 ?50 ?55 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 normalized frequency ( rad/sample) magnitude (db) 11 149-142 figure 139 . fir40 2 i nterpolation filter plot, complete frequency response
ad9119/ad9129 data sheet rev. 0 | page 46 of 68 00 . 4 5 0.400.350.30 0.250.20 0.150.100.05 0.50 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 normalized frequency ( rad/sample) magnitude (db) 11149-143 figure 140. fir40 2 interpolat ion filter plot, pass-band ripple pipeline delay (latency) the pipeline delay, or latency, of the ad9129 varies, based on the configuration that is chosen and can be calculated using the following formula: pipeline_total = pipeline_delay + 2_delay + group_delay + fifo_level the values listed in table 13 can be used, depending on the mode of operation that is selected. table 13. pipeline delay values for each block mode pipeline delay (f dac cycles) group delay (f dac cycles) total pipeline (f dac cycles) total delay (f dac cycles) no 2 filter 74 n/a 74 74 with fir25 43 2 117 119 with fir40 67 9 141 150 the terms used in table 13 are defined as follows: ? pipeline delay is the time from dac code latched until the dac output begins to move. ? group delay is the time for the maximum amplitude pulse to reach the dac output, as compared to the first time the output moves. ? no 2 filter is the base pipeline delay, including data interface, analog circuitry (six cycles), and data fifo at half-full/position 3. ? fir25 is the 2 interpolator with 25 db of out-of-band rejection. ? fir40 is the 2 interpolator with 40 db of out-of-band rejection. note that the values for pipeline delay apply in both normal mode and mix-mode. after the total delay through the digital blocks is calculated, add the fifo level to that delay to find the total pipeline delay. note that the pipeline delay can be considered fixed, with the only ambiguity being the fifo state. the fifo state can be initialized as part of the startup sequence to ensure a four sample spacing and, therefore, a fixed pipeline delay, or deterministic latency (see the resetting the fifo data level section for more information). to ensure repeatable pipeline delay over multiple power-up cycles, the sync output of the dac must be aligned with a known system sync reference. follow a calibration process that is similar to the multiple dac sync process (see the multiple dac synchronization section for more information) after each power-up event to align the dac to the system sync reference. power-up time the ad9119/ ad9129 have a power-down register (register 0x01) that enables the user to power down various portions of the dac. the power-up time for several usage cases is shown in table 14. the recommended way to power up the ad9119 / ad9129 is to power up all parts of the circuit with i ref disabled (by setting register 0x01, bit 6 = 1b), and then enable i ref by programming register 0x01, bit 6 = 0b. table 14. power-up times for several usage cases state register state time (s) power-up from 0x01 = 0xef to 0x01 = 0x08 250 clock path up from 0x01 = 0x0c to 0x01 = 0x08 220 wake-up from 0x01 = 0x48 to 0x01 = 0x08 2 interrupt requests the ad9119/ ad9129 can provide the host processor with an interrupt request output signal (irq), indicating that one or more of the following events has occurred: ? one of the clock controllers has established or lost lock. ? a parity error has occurred. ? a sample error detection status or result is ready. ? the fifo is nearing an overwrite status. the irq output signal is an active low output signal that is available on the irq pin (pin h2). if used, connect the output to vdd via a 10 k pull-up resistor. each irq is enabled by setting the enable bits in register 0x03 and register 0x04 that have the same bit mapping as the irq status bits in registers 0x05 and register 0x06. if an interrupt bit is not enabled, a read request of that bit shows a direct readback of the current state of the source. thus, a read request of either register shows the current state of all eight interrupts in that register, regardless of whether each individual bit is actually enabled to generate an interrupt. when an interrupt bit is enabled, it captures a rising edge of the interrupt source and holds it, even if the source subsequently returns to its zero state. it is possible, for example, for the retimer lost interrupt enable and retimer lock interrupt enable status bits (register 0x03[1:0], respectively) to be set when a controller temporarily loses lock but then reestablishes lock before the irq is serviced by the host. in such a case, the host should validate the present status of the suspect block by reading back its current status bits. based on the status of these bits, the host can take appropriate action, if required.
data sheet ad9119/ad9129 rev. 0 | page 47 of 68 the irq pin respond s only to those interrupts that are enabled. to clear an irq, it is necessary to write a 1 b to the bit in registe r 0x05 or register 0x06 that caused the interrupt. see figure 141 for a detailed diagram of the interrupt circuitry . the irq can also be used during the ad9119 / ad9129 initialization phase after power - up to determine when the retimer pll and data receiver controllers achieve lock. for example, before enabling the retimer pll, the retimer lock interrupt enable bit (register 0x03[0]) can be s et, and the irq output signal can be monitored to det ermine when lock is established, before continuing in a similar manner with the data receiver controller. clear the relevant lock bit , after locking, before continuing to the next controller. when all of the controllers are locked, set the appropriate lost lock enable bits in register 0x0 3 to continuously monitor the controllers for loss of lock. r qd write 1b to request bit irq enable source irq request irq enable irq enable irq pin other irq bits single irq bit 11 149-144 figure 141 . interrupt request circuitry table 15 . interru pt request registers addr (hex) bit bit name description 0x05 7 fifo_warn2 interrupt status indicates that the fifo is within two slots of overwrite 6 fifo_warn1 interrupt status indicates that the fifo is within one slot of overwrite 5 spifrmack inte rrupt status indicates acknowledgement that the sfrmreq bit has changed from 0b to 1b 4 reserved reserved 3 dll warn interrupt status indicates that the dll is close to coming unlocked and action is needed 2 dll lock interrupt status indicates that t he dll is now locked 1 retimer lost interrupt status indicates that the retimer pll is no longer locked 0 retimer lock interrupt status indicates that the retimer pll is now locked 0x06 7 reserved reserved 6 aed pass interrupt status indicates that the aed logic has captured eight valid samples 5 aed fail interrupt status indicates that the aed logic has detected a miscompare 4 sed fail interrupt status indicates that the sed logic has detected a miscompare 3 parity error falling edge status in dicates a parity fault due to data captured on the falling edge 2 parity error rising edge status indicates a parity fault due to data captured on the rising edge 1 reserved reserved 0 reserved reserved
ad9119/ad9129 data sheet rev. 0 | page 48 of 68 i nterface timing vali dation the ad9119 / ad9129 provide on - chip sample error detection (sed) circuitry that simplifies verification of the input data interface. the sed compares the input data samples captur ed at the digital inpu t pins with a set of comparison values. the comparison values are l oaded into registers through the spi port. differences between the captured values and the comparison values are detected and stored. sample error detecti on ( sed ) ope ration the sed circuitry operates on a data set made up of eight 11- bit/14 - bit input words, denoted as r0l, r1l, r0h, r1h, f0l, f1l, f0h, and f1h . these represent the rising edge and falling edge data of data p ort 0 and data port 1. (the ad9119 / ad9129 use both edges of the dci clock to sample data on each input port.) to properly align the input samples, the rising edge data - words of the data ports (that is, rxl and rxh ) are indicated by asserting the frame signal for a minimum of two complete input samples . figure 142 shows the input timing of the interface in word mode. the frame signal can be issued once at t he start of the data transmission, or it can be asserted repeatedly at intervals coinciding with the rxl and rxh data - words. 11149-249 frame p0[7:0] p0[13:8] dci r0l r0h f0l f0h p1[7:0] p1[13:8] r1l r1h f1l f1h figure 142 . timing diagram of frame signal r equired to align input data for sed the sed has three flag b its (register 0x50 , bit 0, bit 1, and bit 2) that indicate the results of the input sample comparisons. the sed fail bit (register 0x50 , bit 0) is set when an error is detected and remains set until cleared. the sed also provides registers that indicate wh ich input data bits experienced errors (register 0x51 through register 0x58 ). these bits are latched and indicate the accumulated errors detected until cleared. to cl e a r the sed registers, write 1b to r egister 0x50 , b it 6. the autosample error d etection (a ed) mode is an autoclear mode that has the following two effects: ? aed mode activates the aed fail bit and the aed pass bit (register 0x50 , bit 1 and bit 2 ). ? aed mode changes the behavior of register 0x51 through register 0x58 . the compare pass bit is set if the last comparison indicates that the sample is error free. the compare fail bit is set if an error is detected. the compare fail bit is automatically cleared by the reception of eight consecutive error - free comparisons. when autoclear mode is enabled, register 0x51 through register 0x58 accumulate errors as previously described but reset to all 0s after eight consecutive error - free sample comparisons are made. the sample error, compare pass, and compare fail flags can be configured to trigger an irq w hen active, if desired. this is accomplished by enabling the appropriate bits in the event flag register (register 0x06 , bit 4, bit 5, and bit 6). sed example normal operation the following example illustrates the sed configuration for continuously monitor ing the input data and assertion of an irq when a single error is detected. 1. write to the following registers to load the comparison values: a) register 0x51 : sed patt/e rr r0l , bits [7:0] . b) register 0x52 : sed patt/e rr r0h , bits [13:8] . c) register 0x53 : sed patt/e rr r1l , bits [7:0] . d) register 0x54 : sed patt/e rr r1h , bits [13:8] . e) register 0x55 : sed patt/e rr f 0l , bits [7:0] . f) register 0x56 : sed patt/e rr f0h , bits [13:8] . g) register 0x57 : sed patt/e rr f1l , bits [7:0] . h) register 0x58 : sed patt/e rr f1h , bits [13:8] . i) comparison values can be chosen arbitrarily; however, choosing v alues that require frequent bit toggling provides the most robust test. 2. enable the sed error detect flag to assert the irq pin. a) register 0x04 : set to 0x10 . 3. begin transmitting the input data pattern. 4. write thr ee times to register 0x50 to enable the sed. a) register 0x50 : set to 0x80 . b) register 0x50 : set to 0xc0 . c) register 0x50 : set to 0x80 . if irq is asserted, read register 0x50 and register 0x51 through register 0x58 to verify that a sed error is detected and deter mine which input bits are in error. the bits in register 0x51 through register 0x58 are latched. this means that the bits i ndicate any errors that occur on those bits throughout the test and not just the errors that cause d the error detected flag to be set .
data sheet ad9119/ad9129 rev. 0 | page 49 of 68 a nalog interface considerations analog modes of oper ation the ad9119 / ad9129 use the quad - switch architecture shown in figure 143 . o nly one pair of switches is enabled during a half - clock cycle , thus requiring each pair to be clocked on alternative clock edges. a key benefit of the quad - switch architecture is that it masks the code - dependent glit ches that occur in the conventional two - switch dac architecture. v g 1 v ssa io utp io utn v g 1 v g 2 v g 3 v g 4 dacc l k_ x clk lat ch es px_d [ 13 :0]x v g 2 v g 3 v g 4 11 149-146 figure 143 . quad - switch architecture in two - switch architecture, when a switch transition occurs and d 1 and d 2 are in different states, a glitch occurs. but, if d 1 and d 2 happen to be at the same state, the switch transitions , and no glitches occur. this code - dependent glitching causes an increased amount o f distortion in the dac. in quad - switch architecture (no matter what the codes are), there are always two switches that are transitioning at each half - clock cycle, thus eliminating the code - dependent glitches but, in the process, creating a constant glitch at 2 dacclk. for this reason, a significant clock spur at 2 f dacclk is evide nt in the dac output spectrum. input da ta dacc l k_ x two -s wit ch dac o utput fo ur -s wit ch dac o utput (normal mode) t d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 6 d 7 d 8 d 9 d 10 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 1 d 2 d 3 d 4 d 5 t 11 149-147 figure 144 . two - switch and quad - switch dac waveforms as a consequence of the quad - switch architecture enabling updates on each half - clock cycle, it is possible to operate that dac core at 2 the dacclk rate if new data samples are latched into the dac core on both the rising and falling edge of the dacclk. this notion serves as the basis when operating the ad9119 / ad9129 in either mix -m ode or with the 2 interpo - lation filter ena bled. in each case, the dac core is presented with new data samples on each clock edge, albeit in mix - mode; the falling edge sample is simply the complement of the rising edge sample value. when mix -m ode is used , the output is effectively chopped at the dac sample rate. this has the effect of reducing the power of the fundamental signal while increasing the power of the images centered around the dac sample rate, thus improving the dynamic range of these images. input da ta da ccl k_ x fo ur -switch d ac output ( f s mix-mode) ?d 6 ?d 7 ?d 8 ?d 9 ?d 10 d 6 d 7 d 8 d 9 d 10 ?d 1 ?d 2 ?d 3 ?d 4 ?d 5 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 1 d 2 d 3 d 4 d 5 t 11 149-148 figure 145 . mix - mode waveform this ability to change modes provides the user the flexibility to place a carrier anywhere in the first three nyquist zones, depending on the operating mode selected. switching between baseband and mix -m ode reshapes the sinc roll - off inheren t at the dac output. in baseband mode, the sinc null appears at f dacclk because the same sample latched on the rising clock edge is also latched again on the falling clock edge , thus resulting in the same ubiquitous sinc res ponse of a traditional dac. in m ix - m ode, the complement sample of the rising edge is latched on the falling edge , therefore pushing the sinc null to 2 f dacclk . figure 146 shows the ideal frequency response of both modes with the sinc roll - off included. normalized f reque nc y relative to f dacclk (hz) 0 1.50 1.25 1.00 0. 75 0. 50 0. 25 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 first nyquist zone second nyquist zone third nyquist zone mix-mode dbfs baseband mode 11 149-149 fi gure 146 . sinc roll - off for baseband mode and mix - mode operation the quad - switch can be configured via spi ( register 0x19 , bit 0 ) to operate in either baseband mod e (0b) or mix - mode (1b).
ad9119/ad9129 data sheet rev. 0 | page 50 of 68 clock input the ad9119 / ad9129 contain a low jitter , differential clock receiver that is capable of interfacin g directly to a differential or single- ended clock source. because the input is self - biased to a nominal mid supply voltage of 1.25 v with a nominal impedance of 10 k? //2 pf, it is recommended that the clock source be ac - coupled to the dacclk _x input pins with an external differential load of 100 ? . wh en the nominal differential input span is 1 v p- p, the clock receiver can operate with a span that ranges from 250 mv p- p to 2.0 v p- p. dacclk_ p to dac and dll da cc lk_n 1. 25 v 5k? 5k? 50 k? 25a duty cycle restorer 11 149-150 figure 147 . clock input the quality of the clock source , as well as its interface to the ad9119 / ad9129 clock input , directly impacts ac performance. select t he phase noise and spur characteristics of the clock source to meet the target application requirements. phase noise and spurs at a given frequency of fset on the clock source are directly translated to the output signal. it can be shown that the phase noise characteristics of a reconstructed output sine wave are re lated to the clock source by 20 log10 (f out /f clk ) when the dac clock path contribution is negligible. (the wideband noise is not dominated by the thermal and quantization noise of the dac .) figure 148 shows a clock source based on the adf4350 low phase noise/jitter pll . the adf4350 can provide output frequencies from 140 mhz up to 4.4 ghz with jitter as low as 0.5 ps rms. its squared - up output level can be varied from ?4 dbm to +5 dbm, allowing further optimization of the c lock drive level. a clock control register exists at address 0x30. this register can be used to enable automatic duty cycle correction (bit 1), enable zero - crossing control (bit 6), and set the zero - crossing point (bits[5:2]). recommended settings for this register are listed in the recommended start - up sequence section (see the start - up sequence section). pll the dacclk _x input goes to a high frequency pll to ensure robust locking of the dac sample clock to the input clock. the pll is en abled by default such that the pll locks upon power -u p. the pll (or dac clock r etimer) control registers are located at register 0x33 and register 0x34. register 0x33 enables the user to set the phase detector phase offset level ( bits[7:4]), clea r the pll lost lock status bit (b it 3), choose the pll di vider for optimum per - formance (b it 2), and c hoose the phase detector mode (bits [1:0]). these settings are determined during product characterization and are given in the recommended start - up sequenc e (see the start - up sequence section). it is not normally necessary to change these values, nor is the product characterization data valid on any settings other than the recommended ones. register 0x34 is used to reset the pll, should that become necessary. at dacclk = 2.8 gsps, the lock time is about 10 s. in most situations, no action is required with the pll. if the dacclk is changed and, especially, if it is changed multiple times, as in a frequency hopping application, a ph ase slip or glitch may be caused by the change in frequency, and it may become necessary to reset the pll. this can be checked by reading the pll retimer lost lock bit (register 0x35, bit 6). if that is the case, toggle the pll reset bit by programming reg ister 0x34, bit 3, high and then low. in addition, clear t he pll retimer lost lock bit by writing 0b to register 0x35 , bit 6. pll l ock can be verified by reading the pll lock bit at register 0x35, bit 7. it is possible to use the irq registers to set an in terrupt for these events. se e the interrupt requests section for more details. vco pll ad f 435 0 f ref 0.8ghz to 2.8ghz 1v p-p 2.4 nf 2.4 nf ad 9 12 9 100 ? d acc l k_ p da cclk_n div-by-2 n n = 0 ? 4 11 149-151 figure 148 . possible signal chain for dacclk _x input
data sheet ad9119/ad9129 rev. 0 | page 51 of 68 voltage reference the ad9119 / ad9129 output current is set by a combination of digital control bits and the i250u reference current, as shown in figure 149. c ur rent scaling fsc[9:0] ad 912 9 da c i fullscale 4k ? 1nf v ref i 25 0 v ssa i 250u v bg 1.0v + ? 11 149-153 figure 149 . volta ge reference circuit the reference current is obtained by forcing the band gap voltage across an external 4.0 k? resistor from i250u (pin a1) to ground. the 1.0 v nominal band gap voltage (vref) generates a 250 a reference current in the 4.0 k? resistor. note the following constraints when configuring the voltage reference circuit: ? both the 4.0 k? resistor and 1 nf bypass capacitor are required for proper operation. ? adjusting the dac output full - scale current, i outfs , from its default setting of 20 ma shou ld be performed digitally. ? the ad9119 / ad9129 are not multiplying dac s . modula - tion of the reference current, i250u, with an ac signal is not supported. ? the band gap voltage appearing at the vref pin must be buffered for use with an external circuitry because its output imped ance is approximately 7.5 k? . ? an external reference can be used to overdrive the internal reference by connecting it to the vref pin. as mentioned, the i outfs can be adjusted digitally over a 9.4 ma to 34.2 ma range by the fsc _x [9:0] bits (register 0x20 , bits[7:0] and register 0x21 , bits [1:0]). the following equation relates i outfs to the fsc _x [9:0] bits, which can be set from 0 to 1023. i outfs = 24.21875 ma fsc _x [9:0] /1000 + 9.4 ma (1) note t hat the default value of 0x200 generates 21.937 ma full scale, but most of the characterization presented in this datasheet uses 3 3 ma, unless noted otherwise . analog outputs equivalent dac output and transfer function the ad9119 / ad9129 provide complementary current outputs, ioutp and ioutn, that sink current from an external load that is referenced to the 1.8 v vdda supply. figure 150 sho ws an equivalent output circuit for the dac. comp ared to most current output dac s of this type, the outputs of the ad9119 / ad9129 exhibit a slight offset current ( t hat is, i outfs /17) , and the peak differential ac current is slightly below i outfs /2 (that is, 8/17 i outfs ). (9/ 17) i outfs i peak = (8/ 17) i outfs i ou tf s = 9.5 ma ? 34ma (9 / 17) i out fs ac 11 149-154 figure 150 . equivalent dac output c ircuit the example shown in figure 150 can be modeled as a pair of dc current sources that source a current of 9/17 i outfs to each output. a differential ac current source, i peak , is used to model the signal ( that is, a digital code) dependent nature of the dac output. the polarity and signal dependency of th is ac current source is related to the digital code (f) by the following equation: f (code) = ( daccode ? 8192)/8192 (2) ?1 < f (code) < +1 (3) where dac code = 0 to 16,383 (decimal). because i peak can swing (8/17) i outfs , the output currents that are me asured at ioutp and ioutn can span from i outfs /17 to i outfs . however, because the ac signal - dependent current component is complementary, the sum of the two outputs is always constant (that is, ioutp + ioutn = (18/17) i outfs ). the code - dependent current that is measured at the ioutp (and ioutn) output is as follows: ioutp = ( 9/17 ) i outfs ( ma ) + ( 8/17 ) i outfs ( ma ) f (code) (4) ioutn = ( 9/17 ) i outfs ( ma ) ? ( 8/17 ) i outfs ( ma ) f (code) figure 151 shows the ioutp vs . daccode transfer function when i outfs is set to 19.65 ma. 20 18 10 12 14 16 output curr ent (ma) 8 6 4 2 0 0 4096 8192 12,288 da c code 16 , 38 4 11 149-155 figure 151 . gain curve for fsc _x [9:0] = 512, dac offset = 1.228 ma
ad9119/ad9129 data sheet rev. 0 | page 52 of 68 peak dac output power capability the maximum peak power capability of a differential current output dac is depen dent on its peak differential ac current, i peak , and the equivalent load resistance it sees. in the case of a 1:1 balun with 50 ? source te rmination, t he equivalent load that is seen by the dac ac current source is 25 ? . if the ad9119 / ad9129 is programmed for an i outfs = 20 ma, its peak ac current is 9.375 ma and its peak power , delivered to the equivalent load , is 2.2 mw ( that is, p = i 2 r). because the source and load resistance seen by the 1:1 balun are equal, this power is shared equally. hence , the output load receive s 1.1 mw, or 0.4 dbm peak power. to calcula te the rms power delivered to the load, consider the following: ? peak - to -r ms of digital waveform ? any digital b ackoff from digital full scale ? dac s inc response and non i deal losses in the external network for example, a reconstructed sine wave with no digita l backoff ideally measure s ? 2.6 dbm because it has a peak - to - rms ratio of 3 db. if a typical balun loss of 0.4 dbm is included , the user would expect to measure ? 3 dbm of actual power in the region where the s inc response of the dac has negligible influenc e. increasing the output power is best accomplished by increasing i outfs . output stage configuration the ad9119 / ad9129 are intended to serve high dynamic range appl ications that require wide signal reconstruction bandwidth (that is, a docsis cable modem termination system ( cmts ) ) and/or high if/ rf signal generation. optimum ac pe rformance can be realized only if the dac output is c onfigured for differential (that is, balanced) operation with its output common - mode voltage biased to a stable, low noise 1.8 v nominal analog supply (vdda). the adp150 ldo can be used to generate a clean 1.8 v supply. the output network used to interface to the dac should provide a near 0 ? dc bias path to vdda. any imbalance in the output impedance over frequency between the ioutp and ioutn pins degrade s the distortion performance (mostly even order) and noise performance. component selection and layout are critical in realizing the perfor mance potential of the ad9119 / ad9129 . most applications that require balanced - to - unbalanced conversion from 10 mhz to 1 ghz can take advantage of the mini - circuits jtx series of transformers that offer impedance ratios of both 2:1 and 1:1. figure 152 shows the ad9119 / ad9129 interfacing to the jtx -2- 10t transformer. this transformer provides excellent amplitude/ phase balance (that is, <1 db/1) up to 1 ghz while providing a 0 ? d dc bias path to vdda. if filtering of the dac images and clock components is required, applying an analog lc filter on th e single - ended side has the advantage of preserving the balance of the transformer . jtx-2-10t+ mini-circuits 50? 50? ioutp ioutn vdda 2:1 11 149-156 figure 152 . recommended transformer for wideband applications with upper bandwidths of u p to 2.2 ghz figure 153 shows an interface that can be considered when interfacing the dac output to a self - biased differential gain block. the inductors (l) shown serve as rf chokes that provide the dc bias path to agnd. its value, along with the dc blocking capacitors, determines th e lower cut - off frequency of the composite pass - band response. (the dc blocking capacitors form a high - pass response with the input resistance of the rf differential gain stage.) 100? ioutp ioutn l l rf diff_ amp c c vdda 11 149-157 figure 153 . interfacing the dac output to self - biased, differential gain stage many rf differential amplifiers consist of two single - ended amplifiers with matched gain , thus providing no common - mode rejection while possibly degrading the balance , due to poor matching characteristics. also, depending on t he component tolerances, differential lc filters can further degrade the balance in a differential signal path. in both cases, the use of a balun could be advantageous in rejecting the common - mode distortion and noise components from the rf dac prior to fi lt ering or further amplification.
data sheet ad9119/ad9129 rev. 0 | page 53 of 68 for applications that operate the ad9119 / ad9129 in mix - mode with output frequencies extending beyond 2.2 ghz, the user may want t o consider the circuit shown in figure 154 . this circuit uses a wideband balun (for example, ?3 db at 4.0 ghz) , with a configuration that is similar to the example shown in figure 152, to provide a dc bias path for the dac outputs. this circuit was implemented on an evaluation board , and the frequency response was measured to compare it with the ideal curve in figure 146. the result is shown in fig ure 155. 50? 50? l l mini-circuits tci-1-13m+ tci-1-33m+ ioutp ioutn c c vdda 11 149-158 figure 154 . recommended mix - mode configuration offering extended rf bandwidth using tc1 -1- 13m + balun ?36 ?33 ?30 ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 power (dbc) frequenc y (mhz) normal mode mix-mode measured normal measured mix-mode 11 149-257 figure 155 . measure d vs. ideal dac output respons e; f dac = 2.6 gsps to assist in matching the ad9119 / ad9129 output, a smith chart is provided in figure 156 . the plot was taken using the circuit in f igure 154 , with the balun and the coupling capacitors removed , and l = 270 nh . for t he measured vs. ideal response of the dac output , see figure 155 , which illustrates that a nonideal response occurs in the second half of the s econd nyquist zone. t his area corresponds to the low impedance area between 2 ghz and 3 ghz , as shown in the smith chart in figure 156 . o utput match ing c an be used to compensate for this nonideal response; t he possible reduction in signal bandwidth must be considered if such match ing is used. 1. 300khz 3.1341 ? 710.55m? 376.96nh 2. 1ghz 54.333? C44.210? 3.5999pf 3. 2ghz 13. 1 13 ? C11.207? 7.1006ph 4. 3ghz 13.022? C14.259? 756.48pf 1 2 3 4 11 149-256 figure 156 . measured smith chart showing the dac output i mpedance ; f dac = 2.6 gsps
ad9119/ad9129 data sheet rev. 0 | page 54 of 68 start - up sequence a small number of steps is required to program the ad9119 / ad9129 to the proper operating state after the device is powered up . this sequence is listed in table 16 , along with an explanation of t he purpose of each step. table 16 . start - up sequence after power -up register value description 0x00 0x00 4- wire spi, msb - first packing, short addressing mode 0x30 0x5c enable cross control, cross lo cation = 7 dec , duty cycle correction off 0x0c 0x64 set dll min imum delay = 4 dec , enable dco 0x0b 0x39 set clock divider to dci/512 0x01 0x68 set b ias power - down 0x34 0x6d or 0x5d set pll mode for normal or 2 mode; n ormal mode or fir25 on = 0x6d , fir 40 on = 0x5d 0x01 0x48 enable bias 0x33 0x13 initialize pll to phase step = 1 dec 0x33 0xf8 or 0xd8 select pfd , set pll phase step, keep pll lost bit cleared; p hase step is as follows: n ormal mode or fir25 on = 0xf8 , fir40 on = 0xd8 0x33 0xf0 or 0xd0 de assert the pll l ost bit, keeping the phase step; n ormal mode or fir25 on = 0xf0 , fir40 on = 0xd0 0x0d 0x06 set duty correction bandwidth to lowest 0x0a 0xc0 enable dll 0x18 0xm0 sel ect d ata mode , filter mode to set value of m; for example: 0x40, unsign ed data, interpolator off 0x20 0xc6 set full - scale c urrent (fsc) to 33 ma 0x21 0x03 complete the setting of fsc 0x30 0x46 enable cross control, cross location = 1 dec , enable duty cycle correction 0x12 0x20 set the fifo pointers 0x11 0x8 1 assert fifo reset 0x11 0x01 de assert fifo reset 0x01 0x00 enable i ref (dac output)
data sheet ad9119/ad9129 rev. 0 | page 55 of 68 device configuration registers device configuration register map the blank b its in table 17 are reserved and should be programmed to their default v alues . a setting of 1 or 0 indicates the required programming for the bit. table 17 . device configuration register map register name address type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault hex dec mode 0x00 0 r/w sdio_dir lsb/msb softreset 0 0 softreset lsb/msb sdio_ dir 0x81 power - down 0x01 1 r/w bg_pd iref_pd bias_pd 1 clkpath_pd retimer_ pd dll _ pd 0x48 irq enable 0 0x03 3 r/w fifo_warn2 fifo_warn1 spi frmack dll w arn dll l ock r etimer l ost r etimer lock 0x00 irq enable 1 0x04 4 r/w aed p ass aed f ail sed f ail parity err f all parity err r ise 0x00 irq request 0 0x05 5 r/w fifo_warn2 fifo_warn1 spi frmack dll w arn dll l ock r etimer l ost retimer lock 0x00 irq request 1 0x06 6 r/w aed p ass aed f ail sed f ail parity err f all parity err r ise 0x00 frame pin usage 0x07 7 r/w parusage frm usage f rm_x pin u sage mode , bits[ 1:0 ] 0x00 reserved_0 0x08 8 r/w must maintain default (reset) value of 0x58 0x58 data ctrl 0 0x0a 10 r/w dll e nable duty cycle correc tion e na ble phase o ffset , bits[3:0] 0x40 data ctrl 1 0x0b 11 r/w warn c lear lock delay d ivider controller clock divider, bits[1:0] delay line middle set, bits[3:0] 0x29 data ctrl 2 0x 0c 12 r/w dco e nable max imum delay set, bits[2:0] minimum delay set , bits [2:0] 0x23 data ctrl 3 0x0d 13 r/w duty correction bw, bits[1:0] 0x04 data stat us 0 0x0e 14 r dll l ock dll w arn dll d elay line start w arn ing d ll d elay line end w arn ing dll correct phase dci on dll lock phase dll r unning n/a fifo c trl 0x11 17 r/w spi frmreq spi frmack ena ble pin f raming phase report e na ble 0x00 fifo offset 0x12 18 r/w rdptroff , bits[2:0] wt ptroff, bits[2:0] 0x04 fifo ph 0 thrm 0x13 19 r phz0thrm, bits[6:0] n/a fifo ph 1 thrm 0x14 20 r phz1thr m, bits[6:0] n/ a fifo p h2 thrm 0x15 21 r phz2thrm, bits[6:0] n/a fifo p h3 thrm 0x16 22 r phz3thrm, bits[6:0] n/a data mode ctrl 0x18 24 r/w filter enable binary select filt_sel 0x00 decode ctrl 0x19 25 r/w mix - mode en 0x00 sync 0x1a 26 r/w inc l atency dec l atency sync e nable sync d one phase r eadback , bits[ 2:0] 0x00 fsc_1 0x20 32 r/w full - scale c urrent , bits[7:0] 0x00 fsc_2 0x21 33 r/w full - scale c urrent , bits[9:8] 0x02 ana_cnt1 0x22 34 r/w 0x00 ana_cnt2 0x23 35 r/w 0x0c c lk reg 1 0x30 48 r/w 0 cross e nable cross l ocation , bits[3:0] duty enable 0 0x00 retime r ctrl 0 0x33 51 r/w phase step , bits[3:0] clear l ost pll divider retime r mode, bits[1:0] 0x30 retime r ctrl 1 0x34 52 r/w pll r eset _z 0x55 ret ime r stat 0 0x35 53 r pll l ock pll l ost n/a sed control 0x50 80 r/w sed e nable sed err or c lear aed e nable 0 0 aed p ass aed f ail sed f ail 0x00 sed patt /err r0l 0x51 81 r sed data port 0 rising edge low part error , bits[7:0] n/a sed patt/err r0h 0x52 82 r sed data port 0 rising edge high part error, bits[13:8] n/a sed patt/err r1l 0x53 83 r sed data port 1 rising edge low part error, bits[ 7:0] n/a sed patt/err r1h 0x54 84 r sed data port 1 rising edge high part error , bits[13:8] n/a sed patt/err f0l 0x55 85 r sed data port 0 falling edge low part error, bits[7:0] n/a sed patt/err f0h 0x56 86 r sed data port 0 falling edge high part error, bits[13:8] n/a sed patt/err f1l 0x57 87 r sed data port 1 falling edge low part error, bits[7:0] n /a sed patt/err f1h 0x58 88 r sed data port 1 falling edge high part error, bits[13:8] n/a parity control 0x5c 92 r/w parity e nable parity e ven parity e rror c lear parity error falling edge parity error rising edge 0x00 parity err rising 0x5d 93 r parity rising edge error count , bits[ 7:0] n/a parity err falling 0x5e 94 r parity falling edge error count , bits[7:0] n/a delay c trl 0 0x70 112 r/w enable delay cell, bits[ 7:0] 0xff delay ctrl 1 0x71 113 r/w enable d elay c ell , bits[ 10:8 ] 0x67 drive s trength 0x7c 124 r/w dco drive strength, bits[ 1:0] 0x7c p art id 0x7f 127 r part id, bits[7:0] 0x07 or 0x87
ad9119/ad9129 data sheet rev. 0 | page 56 of 68 device configuration register d escription s spi communications control register address: 0x00, reset: 0x81, name: m ode table 18 . bit descriptions for m ode bits bit name description r eset access 7 sdio_dir selects 3- wire or 4- wire mode 1: 3 - wire bidirectional 0: 4- wire uni directional 1 r/w 6 lsb/msb lsb/msb data packing 1: lsb - first packing 0: msb - first packing 0 r/w 5 so ftreset 1: performs a software - based reset 0 r/w 4 reserved must be set to 0; reserved (s hort addressing mode) 0 r/w 3 reserved mirror bit 4 for s afety 0 r 2 softreset mirror bit 5 for safety 0 r 1 lsb/msb mirror bit 6 for safety 0 r 0 sdio_dir mirror bit 7 for safety 1 r power control register address: 0x01 , reset: 0x48, name: power -d own table 19 . bit descriptions for power - down bits bit name description reset access 7 bg_pd band gap power - down 1: b and gap is power ed down 0: b and gap is active 0 r/w 6 i ref_pd i ref power - down 1: fsc is 0 ma 0: fsc is as programmed 1 r/w 5 bias_pd bias power - down 1: all b ias currents are off 0: all b ias currents are on 0 r/w 4 r eserved reserved 0 r/w 3 reserved m ust be set to 1 ; reserved 1 r/w 2 clkpath_pd clock path power - down 1: dac c lock is powered down 0: dac c lock is active 0 r/w 1 retimer_ pd 1: pll is power ed down 0 r/w 0 dll_pd dll (d ata receiver ) power - down 1: dll ( data r eceiver ) is powered down 0 r/w
data sheet ad9119/ad9129 rev. 0 | page 57 of 68 interrupt enable register 0 a ddress: 0x03 , reset: 0x00, name: irq enable 0 table 20 . bit descriptions for irq enable 0 bits bit name description reset access 7 fifo_ warn 2 interrupt enable enables the fifo warning within two slots of overwrite interrupt 0 r/w 6 fifo_ warn1 interrupt e nable e nables the fifo warning within one slot of overwrite interrupt 0 r/w 5 spi frm ack interrupt e nable enables the fifo spi - based calibration acknowledgement of spi frmreq (address 0x11, bit 7) going from 0 b to 1b 0 r/w 4 reserved r eserved 0 r 3 dll w arn interrupt e nable enables the dll w arning flag that the d ata r eceiver is no longer locked 0 r/w 2 dll l ock interrupt e nable enables the dll w arning flag that the data r eceiver is now locked 0 r/w 1 retimer l ost interrupt e nable ena bles the retimer lost i nterrupt indication 0 r/w 0 retimer l ock interrupt e nable enables the retimer lock interrupt indication 0 r/w interrupt enable register 1 address: 0x04, reset: 0x00, name: irq enable 1 table 21 . bit descript ions for irq enable 1 bits bit name description reset access 7 reserved reserved 0 r/w 6 aed p ass interrupt e nable enables the aed pass i nterrupt reporting saying that eight valid s amples captured 0 r/w 5 aed f ail interrupt enable enables the aed fail i nterrupt reporting that a mis compare occurred 0 r/w 4 sed f ail interrupt enable enables the sed fail interrupt reporting that a miscompare occurred 0 r/w 3 parity error falling edge enable enables the parity fail due to a falling edge - based parity detect ed error 0 r/w 2 parity error rising edge enable enables the parity fail due to a rising edge - based parity detected error 0 r / w 1 reserved reserved 0 r 0 reserved reserved 0 r interrupt status register 0 address: 0x05, reset: 0x00, name: irq request 0 table 22 . bit descriptions for irq request 0 bits bit name description reset access 7 fifo_ warn2 interrupt status indicates that the fifo is within two slots of overwrite 0 r 6 fifo_ warn1 interrupt status ind icates that the fifo i s within one slot of overwrite 0 r 5 spifrm ack interrupt status indicates acknowledgement of spi frmreq has changed from 0 b to 1b 0 r 4 reserved reserved 0 r 3 dll w arn interrupt status indicates that the dll ( data r eceiver) is close to coming unlocked and action is needed 0 r 2 dll l ock interrupt status indicates that the dll ( data r eceiver ) is now locked 0 r 1 retimer lost interrupt status indicates that the r etime r pll is no longer locked 0 r 0 retimer l ock interrupt status indicates that the r etime r pll is now locked 0 r
ad9119/ad9129 data sheet rev. 0 | page 58 of 68 interrupt status register 1 address: 0x06, reset: 0x00, name: irq request 1 table 23 . bit descriptions for irq r equest 1 bits bit name description reset access 7 reserved reserved 0 r/w 6 aed p ass interrupt s tatus indicates that the aed logic has captured eight valid samples 0 r/w 5 aed fail interrupt status indicates that t he aed logic has detected a mis compare 0 r/w 4 sed fail interrupt status indicates that the sed logic has detected a miscompare 0 r/w 3 parity error falling edge s tatus indicates a p arity fau lt due to data captured on the falling e dge 0 r/w 2 parity error rising edge s tatus indicates a p arity fau lt due to data captured on the rising e dge 0 r/w 1 reserved reserved 0 r/w 0 reserved reser ved 0 r/w frame pin usage register address: 0x07, reset: 0x00, name: frame pin usage table 24 . bit descriptions for frame pin usage bits bit name description reset access 7 reserved reserved 0 r/w 6 reserved reserved 0 r / w 5 paru sage 1: frm _x pin is in parity mode , and parity is e nabled note that p arity must be enab led , and the type must be chosen in r egister 0x5c[7:6] 0 r 4 frm usage 1: frm _x pin is in f rame mode and enable pin framing ( register 0x11[5] = 1 b ) is enabled 0 r 3 re served reserved 0 r 2 reserved reserved 0 r [1:0] frm_x pin usage mode 3: reserved 2: frame 1: parity 0: no e ffect 0x0 r/w reserved _0 register address: 0x08, reset: 0x58, name: r eserved _0 table 25 . bit descriptions for reserved _0 bits bit name description reset access [7:0] reserved m ust keep default (reset) v alue ; reserved 0x58 r data receiver control 0 register address: 0x0a, reset: 0x40, name: data ctrl 0 table 26 . bit descriptions for data ctrl 0 bits bi t name description reset access 7 dll e nable 1: e nable s dll 0: d isable s dll 0 r/w 6 duty cycle correction e nable 1: e nable s duty cycle c orrection 0: disable s duty cycle c orrection 1 r/w 5 reserved reserved 0 r/w 4 reserved reserved 0 r / w [3:0] phase o ffset locked phase = 90 n 11.25, where n is the 4 - bit signed magnitude number 0x0 r/w
data sheet ad9119/ad9129 rev. 0 | page 59 of 68 data receiver control 1 register address: 0x0b, reset: 0x29, name: data ctrl 1 table 27 . bit descriptions for data ctrl 1 bits bit name de scription reset access 7 warn clear 1: c lear s data receiver w arn ing b it 0 r/w 6 lock delay d ivider 1: long delay 0: short delay 0 r/w [5:4] controller clock d ivider controller c l ock divider 00: dci/4 01 : dci/16 10 : dci/64 11 : dci/512 0x2 r/w [3:0] del ay line middle s et sets nominal delay line delay 0x9 r/w data receiver control 2 register address: 0x0c, reset: 0x23, name: data ctrl 2 table 28 . bit descriptions for data ctrl 2 bits bit name description reset access 7 reserved res erved 0 r/w 6 dco e nable 1: enables dco output d river 0 r/w [5:3] max imum delay s et sets m ax imum delay line d elay (larger number = longer delay line) 0x2 r/w [2:0] min imum delay set sets minimum delay line delay (larger number = smaller delay line) 0x3 r/w data receiver control 3 register address: 0x0d, reset: 0x04, name: data ctrl 3 table 29 . bit descriptions for data ctrl 3 bits bit name description reset access [7:3] reserved reserved . 0x00 r [2:1] duty correction bw set contr oller clock divider . 00: h ighest bw . 01: h igher bw . 10: l ower bw . 11: l owest bw . 0x2 r/w 0 reserved reserved 0 r/w data receiver status 0 register address: 0x0e, reset: 0x00, name: d ata s tatus 0 table 30 . bit descriptions for d ata s tatus 0 bits bit name description reset access 7 dll lock 1: dll lock 0 r 6 dll warning 1: dll near begin n ing/end of delay line 0 r 5 dll delay line start warning 1: dll at beginning of delay line 0 r 4 dll delay line end warning 1: dll at end of dela y line 0 r 3 dll correct phase 1: d ata is sampled on correct phase 0 : data is sampled on incorrect phase. 0 r 2 dci on 1: user has provided a clock > 100 mhz 0 r 1 dll l ock phase 1: dll is locked on negative half of dci. 0: dll is locked on positive hal f of dci 0 r 0 dll running 1: closed loop dll attempting to lock 0: d elay fixed at middle of delay line 0 r
ad9119/ad9129 data sheet rev. 0 | page 60 of 68 fifo control register address: 0x11, reset: 0x00, name: fifo ctrl table 31 . bit descriptions for fifo ctrl bits bit name d escription reset access 7 spifrmreq requests a spi - based fifo alignment (fifo reset ) 0 r/w 6 spifrmack acknowledge s spifrmreq change (tracks spifrmreq setting) 0 r/w 5 enable pin f ram ing 1: enables hardware pin - based fifo f raming 0 r/w [4:1] reserved r eserved 0x0 r 0 phase r ep ort enable 1: enables fifo phase reporting 0 r/w fifo offset register address: 0x12, reset: 0x04, name: fifo offset table 32 . bit descriptions for fifo offset bits bit name description reset access 7 reserved reserved 0 r [6:4] rdptroff[2:0] fifo read pointer offset 0x0 r/w 3 reserved reserved 0 r [2:0] wtptroff[2:0] fifo write pointer offset 0x4 r/w fifo thermometer for phase 0 status register address: 0x13 , reset: 0x00, name: fifo p h0 thrm table 33 . bit descriptions for fifo p h0 thrm bits bit name description reset access 7 reserved reserved 0 r [6:0] phz0thrm phase 0- based fifo thermometer status. phase 0 relative fifo p hasing, as 0000000 b to 1111111 b , where 00000 11 b is conside red the middle of the fifo storage space . 0x00 r fifo thermometer for phase 1 status register address: 0x14 , reset: 0x00, name: fifo p h1 thrm table 34 . bit descriptions for fifo p h1 thrm bits bit name description reset access 7 reserved reserved 0 r [6:0] phz1thrm phase 1 - based fifo thermometer status . phase 1 relative fifo p hasing , as 0000000 b to 1111111 b, where 0000011 b is considered the middle of the fifo storage space . 0x00 r fifo thermometer for phase 2 status register add ress: 0x15, res et: 0x00, name: fifo p h2 thrm table 35 . bit descriptions for fifo p h2 thrm bits bit name description reset access 7 reserved reserved 0 r [6:0] phz2thrm phase 2 - based fifo thermometer status . phase 2 relative fifo p ha sing, as 0000000 b to 1111111 b, where 0000011 b is considered the middle of the fifo storage space . 0x00 r fifo thermometer for phase 3 status register address: 0x16, reset: 0x00, name: fifo p h3 thrm table 36 . bit descriptions for fifo p h3 thrm bits bit name description reset access 7 reserved reserved 0 r [6:0] phz3thrm phase 3 - based fifo thermometer status . phase 3 relative fifo p hasing , as 0000000 b to 1111111 b, where 0000011 b is considered the middle of the fifo storage space . 0x00 r
data sheet ad9119/ad9129 rev. 0 | page 61 of 68 data mode control register address: 0x18, reset: 0x00, name: data mode ctrl table 37 . bit descriptions for data mode ctrl bits bit name description reset access 7 filter e nable 1: enables 2 interpolation filter 0: bypass es 2 i nterpolation filter 0 r/w 6 binary s elect select s input data format 1: unsigned 0: signed 0 r/w 5 filt_sel 2 interpolator filter select 1: 40 db oob rejection 0: 25 db out - of -b and (oob) rejection 0 r [4:0] reserved reserved 0 r decoder control (progra m thermometer type) register address: 0x19, reset: 0x00, name: decode ctrl table 38 . bit descriptions for decode ctrl bits bit name description reset access [7:1] reserved reserved 0x00 r 0 mix - mode e nable 1: mix -m ode 0: n ormal 0 r/w sync control register address: 0x1a, reset: 0x00, name: sync table 39 . bit descriptions for sync bits bit name description reset access 7 inc latency increment delay by 1 0 r/w 6 dec latency decrement delay by 1 0 r/w 5 reserved reserved 0 r 4 sync enable 1: multi - dac sync output pin enabled 0: m ulti - dac sync output pin disabled 0 r / w 3 sync done 1: last increment or decrement request is complete 0 r [2:0] ph ase readback readback of existing sync phase delay value 0 r full - sc ale current adjust (lower) register address: 0x20, reset: 0x00, name: fsc_1 table 40 . bit descriptions for fsc_1 bits bit name description reset access [7:0] full - scale current, bits [7:0] dac gain adj ust ; dac full - scale current (lsb ) 0x00 r/w full - scale current adjust (upper) register address: 0x21 reset: 0x02, name: fsc_2 table 41 . bit descriptions for fsc_2 bits bit name description reset access 7 reserved reserved 0 r/w [6:2] reserved reserved 0 r [ 1:0 ] fu ll- scale current, bits [9:8] dac gain adj ust ; dac full - scale current (msb ) 0x02 r/w
ad9119/ad9129 data sheet rev. 0 | page 62 of 68 analog control 1 register address: 0x22, reset: 0x00, name: ana_cnt1 table 42 . bit descriptions for ana_cnt1 bits bit name description reset access [ 7:0] reserved reserved 0x0 r/w analog control 2 register address: 0x23, reset: 0x0c, name: ana_cnt2 table 43 . bit descriptions for ana_cnt2 bits bit name description reset access [7:0] reserved reserved 0x0c r/w clock control 1 reg ister address: 0x30, reset: 0x00, name: clk reg1 table 44 . bit descriptions for clk reg1 bits bit name description reset access 7 reserved must be set to 0 ; reserved 0 r/w 6 cross enable enable s zero - cross ing control 0 r/w [5:2] cr oss location adjust s zero - cross ing control location ( signed magnitude ) 0 r/w 1 duty enable enable s duty cycle correction 0 r/w 0 select internal must be set to 0 0 r/w retimer control 0 register address: 0x33, reset: 0x30, name: retime r ctrl 0 table 45 . bit descriptions for retime ctrl 0 bits bit name description reset access [7:4] phase step 4- bit sign ed magnitude; pfd p hase step = n 30 0x3 r/w 3 clear lost clear lost status bit 0 2 pll divider 1 : d ivide -by -4 0: d ivide -by -8 0 [1:0] retime r mode 0: enable pfd , normal mode 1: reserved 2: reserved 3: reserved 0x0 retimer control 1 register address: 0x34, reset: 0x55, name: retime r ctrl 1 table 46 . bit descriptions for retime r ctrl 1 bits bit name description reset access [7:4] reserved reserved 0x5 r/w 3 pll reset _z 1: normal operation for dac clock pll 0: resets the dac clock pll 0 r/w [2:0] reserved reserved 0x5 r/w retimer status 0 register address: 0x35, reset: 0x00, name: r etime r stat 0 table 47 . bit descriptions for r etime r stat 0 bits bit name description reset access 7 pll l ock 1: r etimer pll l ocked 0 r 6 pll l ost 1: r etimer pll lost (c an be sticky) 0 r [5:4] reserved reserved 0x0 r [3:0] reserved reserved 0x0 r
data sheet ad9119/ad9129 rev. 0 | page 63 of 68 samp le error detection (sed) control register address: 0x50, reset: 0x00, name: sed control table 48 . bit descriptions for sed control bits bit name description reset access 7 sed enable 1 : setting this bit to 1 e nable s the sed compare l ogic 0 r/w 6 sed error clear 1: clears all sed reported error bits below 0 r/w 5 aed enable 1: enables t he aed function ( sed with auto cl ear after eight passing sets) 0 r/w 4 reserved m ust be set to 0 ; reserved 0 r 3 reserved must be set to 0; reserved 0 r 2 aed pass 1: s ignals eight true compare cycles 0 r/w 1 aed fail 1: signals a mis compare 0 r 0 sed fail 1: signals an sed mis compare (w ith sed or aed enabled) 0 r sample error detection (sed) data port 0 rising edge status low register address: 0x5 1, reset: 0x00, name: sed patt/err r0l table 49 . bit descriptions for sed patt/err r0l bits bit name description reset access [7:0] sed data port 0 rising edge low part error bits sed data port 0 rising edge e rror , bits[7:0] 0x00 r sample error detection (sed) data port 0 rising edge status high register address: 0x52 , reset: 0x000, name: sed patt/err r0h table 50 . bit descriptions for sed patt/err r0h bits bit name description reset access [7:6] reserved reser ved 0x0 r [5:0] sed data port 0 rising edge high part error bits sed data port 0 rising edge error, bits[13:8] 0x00 r sample error detection (sed) data port 1 rising edge status low register address: 0x53, reset: 0x00, name: sed patt/err r1l table 51 . bit descriptions for sed patt/err r1l bits bit name description reset access [7:0] sed data port 1 rising edge low part error bits sed data port 1 rising edge error, bits[7:0] 0x00 r sample error detection (sed) data port 1 rising edg e status high register address: 0x54, reset: 0x00, name: sed patt/err r1h table 52 . bit descriptions for sed patt/err r1h bits bit name description reset access [7:6] reserved reserved 0x0 r [5:0] sed data port 1 rising edge high pa rt error b its sed data port 1 rising edge error, bits[13:8] 0x00 r
ad9119/ad9129 data sheet rev. 0 | page 64 of 68 sample error detection (sed) data port 0 falling edge status low register address: 0x55, reset: 0x00, name: sed patt/err f0l table 53 . bit descriptions for sed patt/err f0l bits bit name description reset access [7:0] sed data port 0 falling edge low part error bits sed data port 0 falling edge error, bits[7:0] 0x00 r sample error detection (sed) data port 0 falling edge status high register address: 0x56, reset: 0x0 00, name: sed patt/err f0h table 54 . bit descriptions for sed patt/err f0h bits bit name description reset access [7:6] reserved reserved 0x0 r [5:0] sed data port 0 falling edge high part error bits sed data port 0 falling edge err or, bits[13:8] 0x00 r sample error detection (sed) data port 1 falling edge status low register address: 0x57, reset: 0x00, name: sed patt/err f1l table 55 . bit descriptions for sed patt/err f1l bits bit name description reset access [7:0] sed data port 1 falling edge low part error bits sed data port 1 falling edge error, bits[7:0] 0x00 r sample error detection (sed) data port 1 falling edge status high register address: 0x58, reset: 0x00, name: sed patt/err f1h table 56 . bit descriptions for sed patt/err f1h bits bit name description reset access [7:6] reserved reserved 0x0 r [5:0] sed data port 1 falling edge high part error bits sed data port 1 falling edge error, bits[13:8] 0x00 r parity control register address: 0x5c, reset: 0x00, name: parity control table 57 . bit descriptions for parity control bits bit name description reset access 7 parity e nable 1 : e nable s p arity 0x00 r/w 6 parity e ven 1: even parity; if the parity bit from the frm_x pin = 1, the number of 1s in the word is even 0: o dd parity ; if the parity bit from the frm_x pin = 1 , the number of 1 s in the word is odd note that the p arity bit mus t be enabled in r egister 0x07 0 r/w 5 parity error c lear 1 : clear s parity error counters 0 r/w [4:2] reserved reserved 0x0 r 1 parity error falling edge 1: signals detection of a falling edge parity error 0 r 0 parity error rising edge 1: signals detection of a rising edge parity error 0 r parity rising edge count register addres s: 0x5d, reset: 0x00, name: parity err rising table 58 . bit descriptions for parity err rising bits bit name description reset access [7:0] parity rising edge error count number of rising edge -b ased errors detected , clipped to 256 0x00 r parity falling edge count register address: 0x5e, reset: 0x00, name: parity err falling table 59 . bit descriptions for parity err falling bits bit name description reset access [7:0] parity falling edge error count number of fa lling edge - based errors detected , clipped to 256 0x00 r
data sheet ad9119/ad9129 rev. 0 | page 65 of 68 delay control register 0 address: 0x70, reset: 0xff, name: delay ctrl 0 table 60 . bit descriptions for delay ctrl 0 bits bit name description reset access [7:0] e nable delay ce ll set s each bit to enable or disable the delay cell, bits[7:0]; d elay cell number corresponds to bit number 1 : e nable s delay cell (default) 0: d isable s delay cell 0xff r/w delay control register 1 address: 0x71, reset: 0x67, name: delay ctrl 1 table 61 . bit descriptions for delay ctrl 1 bits bit name description reset access [7:3] reserved reserved 0x60 r/w [2:0] enable delay cell sets each bit to enable or disable the delay cell , bits[10:8] ; delay cell numbers are 10, 9, and 8, wh ich correspond to bit 2, bit 1, and bit 0, respectively 1: enables delay cell (default) 0: disables delay cell 0x7 r/w drive strength register address: 0x7c, reset: 0x7c, name: drive strength table 62 . bit descriptions for drive stre ngth bits bit name description reset access [7:6] dco drive s trength sets dco drive strength 00: 2 ma 01: 2.8 ma (default) 10: 3.4 ma 11: 4 ma 0x1 r/w [5:0] reserved reserved 0x3c r/w part id register address: 0x7f, reset: 0x03 or 0x83, name: part id ta ble 63 . bit descriptions for part id bits bit name description reset access [7:0] part id version i nformation 0x07 = the ad9129 (14 - bit version) 0x87 = the ad9119 (11 - bit version) 0x07 or 0x87 r
ad9119/ad9129 data sheet rev. 0 | page 66 of 68 outline dimensions 12.10 12.00 sq 11.90 0.43 max 0.25 min 1.00 max 0.85 min a b c d e f g h j k l m n p 14 13 12 11 10 8 7 6 3 2 1 9 5 4 1.40 max 0.55 0.50 0.45 10.40 bsc sq 1 1-18-20 1 1- a compliant with jedec s t andards mo-275-ggaa-1. coplanarit y 0.12 ball diameter 0.80 bsc de t ai l a a1 ball corner a1 ball corner detail a bottom view top view seating plane figure 157 . 160 - ball chip scale package ball grid array [csp_bga] (bc- 160 - 1) dimensions shown in millimeters ordering guide model 1 temperature range pac kage description package option ad9119bbcz ?40 c to +85c 160- ball chip scale package ball grid array [csp_bga] bc -160 -1 ad9119bbczrl ?40c to +85c 160- ball chip scale package ball grid array [csp_bga] bc -160-1 ad9119 - ebz evaluation board for normal mode evaluation ad9119 - mix - ebz evaluati on board for mix - m ode evaluation ad9119 - c b lt x - ebz evaluation board for cable transmitter evaluation ad9129bbcz ?40c to +85c 160- ball chip scale package ball grid array [csp_bga] bc -160 -1 ad9129bbczrl ?40c to +85c 160 - ball chip scale package bal l grid array [csp_bga] bc - 160 - 1 ad9129bbc ?40c to +85c 160- ball chip scale package ball grid array [csp_bga] bc -160 -1 ad9129bbcrl ?40c to +85c 160- ball chip scale package ball grid array [csp_bga] bc -160-1 ad9129 - ebz evaluation board for normal mode evaluation ad9129 - mix - ebz evaluation board for mix -m ode evaluation ad9129 - c b lt x - ebz evaluation board for cable transmitter evaluation 1 z = rohs compli ant part.
data sheet ad9119/ad9129 rev. 0 | page 67 of 68 notes
ad9119/ad9129 data sheet rev. 0 | page 68 of 68 notes ? 2013 analog devices, inc. all rights reserved. trademarks a nd registered trademarks are the property of their respective owners. d11149 -0- 1/13(0)

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